Commit Graph

4672 Commits

Author SHA1 Message Date
Yilou Wang cd6d2e769c
Merge a5e8e1df32 into a0b89dde8e 2026-02-15 10:04:43 +01:00
Geza Lore be27811a10
Optimize: Remove redundant variables during Dfg Peephole pass (#7076)
Many rules in the Dfg Peephole pass check if a node has more than one
sinks. Redundant variables that will ultimately be removed can prevent
these from matching. Remove such variables during the Peeophole pass
itself to enable more matches.
2026-02-14 12:33:20 +00:00
Geza Lore a45a058b09
Optimize additional DFG peephole Shift and Concat patterns (#7077) 2026-02-14 07:25:17 -05:00
Geza Lore e0c626e48a
Fix constant propagating DPI-written variables (#7074) 2026-02-13 18:28:14 +00:00
Igor Zaworski 7d71c3bb76
Fix of event triggering with V3Life (#6932 effect) (#7068 partial) (#7072) 2026-02-13 11:01:19 -05:00
Pawel Kojma 64511d30b6
Internals: Fix marking `AstVar`s as class members (#7070) 2026-02-13 07:45:13 -05:00
Geza Lore 3dd2b762e7
Fix scope tree in traces in hierarchical mode (#7042) 2026-02-12 20:54:03 -05:00
Veripool API Bot b0fdbff6eb Verilog format 2026-02-12 18:23:56 -05:00
Yilou Wang a5e8e1df32 Support randc enum variables with user constraints in solver
When randc enum variables have user constraints, they go through the
SMT solver path which treats them as unconstrained bitvectors. This
adds implicit enum membership constraints so the solver only produces
valid enum member values.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-12 17:53:30 +01:00
Todd Strader fed41aba91
Fix UNUSED / UNDRIVEN for unused functions (#6967) 2026-02-12 11:01:14 -05:00
Yilou Wang 9b1b9a5b3b
Fix randc cyclic behavior broken with constraints (#7029) (#7035) 2026-02-12 10:58:04 -05:00
Yilou Wang c28119e51d Fix enum variables in constraint solver producing invalid enum values
When enum variables (rand or randc) are referenced in user constraints,
the constraint solver declares them as unconstrained bitvectors, which
can produce values outside the valid enum range. Add implicit membership
constraints to restrict solver output to valid enum members
(IEEE 1800-2017 §18.4.2).

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-12 13:44:46 +01:00
Igor Zaworski 446bec3d1a
Fix event triggering (#6932) 2026-02-11 10:35:59 -08:00
Yilou Wang e41436bd4a
Support inherited and nested pre/post_randomize callbacks (#7049) (#7053) 2026-02-11 09:33:57 -08:00
Yilou Wang 554fcef627
Fix rand_mode()/constraint_mode() when used as function arguments (#7051) (#7055) 2026-02-11 09:33:09 -08:00
Yilou Wang 996a4b6e1a
Fix constraint_mode()/rand_mode() in constructor being overwritten by init code (#7054) 2026-02-11 09:32:08 -08:00
Yilou Wang 84350859e0
Support System Functions in Constraint Blocks (#7028) (#7036) 2026-02-11 05:19:25 -08:00
Pawel Kojma 5d12ae3a2f
Fix non-member identifiers used inside constraints (#7033) 2026-02-11 05:18:24 -08:00
Yilou Wang 22dc437dbb
Support std::randomize() for queue, dynamic array, and associative array variables (#7044) 2026-02-10 18:24:25 -08:00
Wilson Snyder 67bff893bf Fix whitespace 2026-02-10 20:17:22 -05:00
Yilou Wang 2bb807a931
Fix Inline foreach constraints on dynamic arrays of class objects (#7030) (#7037) 2026-02-10 15:22:31 -08:00
Geza Lore a031dd1a22
Fix tracing without module inlining to match with inlining (#7041)
This is an attempt to generate an identical trace file scope hierarchy
both with and without -fno-inline. Primarily because it's needed for
testing in upcoming patch, but also improves consitency prior to #7001
2026-02-10 21:05:41 +00:00
Yilou Wang 925543676e
Fix rand_mode() on nested object variables causes Z3 solver error (#7031) (#7034) 2026-02-10 13:59:09 -05:00
Yilou Wang 8791e6c5f2
Support constraint_mode() on static constraints (#7027) (#7038) 2026-02-10 13:58:35 -05:00
Ryszard Rozak 6303eb45ce
Fix multidim dynamic array elements passed to ref argument (#7023) 2026-02-10 08:46:04 +01:00
Igor Zaworski a660fa54a7
Fix unique constraint in derived class (#7022) 2026-02-09 09:56:38 -05:00
github action a28bd5a085 Apply 'make format' 2026-02-09 03:48:11 +00:00
Leela Pakanati e36838ad8e
Fix tristate enables for -fno-inline (#7016) (#7019) 2026-02-08 22:47:09 -05:00
Wilson Snyder 5a236dd35d
Change INITIALSTATIC to also report on processes, per IEEE (#7020) 2026-02-08 20:47:12 -05:00
Wilson Snyder ba194f3790 Tests: Avoid implied static variables, to avoid future warning 2026-02-08 18:20:28 -05:00
Wilson Snyder 9ba625225d Internals: Minor cleanups preparing for initialization fixes. No functional change. 2026-02-08 17:54:04 -05:00
Wilson Snyder 8700617fae Internals: Cleanup CRESET verilog and other misc fixes 2026-02-08 17:53:56 -05:00
Wilson Snyder e12c62c070 Change JSON dumps to not include booleans that are false (#6977).
Fixes #6977.
2026-02-08 07:59:55 -05:00
Wilson Snyder 0c83594e1e Fix variable conflict when multiple cells with unused input defaults 2026-02-07 18:11:55 -05:00
Wilson Snyder bbb231dfe2 Internals: Minor cleanups preparing for initialization fixes. No functional change. 2026-02-07 14:16:12 -05:00
Geza Lore bb0e1c8c61
Optimize temporary insertion for concatenations in Dfg (#7013)
Add a new Dfg pass 'pushDownSel'. This will try to move selects through
a tree of concatenations in order to eliminate temporary nodes holding
intermediate concatenation results. This can get rid of a lot of
variables when packed arrays are assigned in parts (e.g. bit-wise).
2026-02-07 18:06:12 +00:00
github action abdac02b50 Apply 'make format' 2026-02-07 15:07:33 +00:00
Leela Pakanati 8922794088
Tests: Add test cases for interface array access with loop variable index (#1418 tests) (#7011) 2026-02-07 10:06:37 -05:00
Igor Zaworski dc26dd601d
Fix internal error - virtual interface not found (#7010) 2026-02-06 22:20:10 +00:00
Pawel Kojma 9a8538fafa
Support signed multiplication in constraints (#7008) 2026-02-06 10:14:54 -05:00
github action 60b52a4986 Apply 'make format' 2026-02-06 11:39:13 +00:00
Leela Pakanati b14d65a787
Support modport expression syntax + nested (#2601) (#5581) (#7005) 2026-02-06 06:38:16 -05:00
Leela Pakanati 2215d01d6b
Fix hierarchical interface/modport issues (#5941) (#6997) 2026-02-05 22:15:30 -05:00
Veripool API Bot b82f6beffb Verilog format 2026-02-05 17:45:24 -05:00
Wilson Snyder 9fab6bfcf0 Tests: Fix t_assert_elab_p.py reruns 2026-02-05 17:42:39 -05:00
Wilson Snyder 1adedd0bfa Tests: Cover deassign 2026-02-05 12:57:26 -05:00
Geza Lore 4e9792c34c
Fix C++ types of non-inlined module ports (#7002)
We use special C++ types for ports, e.g. SystemC types in --sc mode, and native C arrays for unpacked arrays in --cc mode. These types are not substitutable for internal types, e.g. VlUnpacked, however all the runtime primitives expect internal types.

I think the intention was to use these special IO types only for top level ports, but the current implementation also uses them for the ports of all non-inlined modules. This means the output C++ will not compile if such a port is passed to a runtime primitive (e.g. array 'sort' as in the new test) or DPI import.

Changed to use the special IO types only on the top level ports.

Note these are likely still broken if attempting to invoke on a top level port (we might be saved by wrapTop, but later optimizations might eliminate the intermediary)
2026-02-05 14:49:07 +00:00
github action 55eaa64386 Apply 'make format' 2026-02-04 21:27:14 +00:00
Leela Pakanati 57c3b8e51b
Support nested interface as port connection (#5066) (#6986) 2026-02-04 16:26:20 -05:00
Oleh Maksymenko 229a696ab8
Add decoded Verilog name in JSON output (#6919) (#6995) 2026-02-04 07:08:33 -05:00