luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,410 Commits 31 Branches 4 Tags 7.7 MiB
Commit Graph

2410 Commits

Author SHA1 Message Date
Tim Ansell b13dc8bc5b
Merge pull request #951 from SymbiFlow/dependabot/submodules/third_party/abseil-cpp-f3840bc 
build(deps): bump third_party/abseil-cpp from `44efe96` to `f3840bc`
 2019-07-21 16:10:30 -04:00
Tim Ansell 887d9582e2
Merge pull request #952 from SymbiFlow/dependabot/submodules/third_party/googletest-b77e5c7 
build(deps): bump third_party/googletest from `ee3aa83` to `b77e5c7`
 2019-07-21 16:10:13 -04:00
dependabot-preview[bot] f1bf235c4a
build(deps): bump third_party/googletest from `ee3aa83` to `b77e5c7` 
Bumps [third_party/googletest](https://github.com/google/googletest) from `ee3aa83` to `b77e5c7`.
- [Release notes](https://github.com/google/googletest/releases)
- [Commits](ee3aa83117...b77e5c7625)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
 2019-07-20 05:13:36 +00:00
dependabot-preview[bot] 9be29a391a
build(deps): bump third_party/abseil-cpp from `44efe96` to `f3840bc` 
Bumps [third_party/abseil-cpp](https://github.com/abseil/abseil-cpp) from `44efe96` to `f3840bc`.
- [Release notes](https://github.com/abseil/abseil-cpp/releases)
- [Commits](44efe96dfc...f3840bc5e3)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
 2019-07-20 05:13:17 +00:00
litghost 55e0ca77c7
Merge pull request #936 from antmicro/891_hclk_ioi_pips 
Add fuzzer for HCLK_IOI3 PIPs
 2019-07-19 09:33:30 -07:00
Tomasz Michalak 35ee0830a7 047-hclk-ioi-pips: Add targeted todo list routing to vivado script 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-19 08:19:00 +02:00
Tomasz Michalak 8aaef604cb 047-hclk-ioi-pips: Filter out PIPs that are not being solved currently 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-19 08:19:00 +02:00
Tomasz Michalak 727d5ca377 fuzzers: Add fuzzer for HCLK_IOI3 PIPs 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-19 08:19:00 +02:00
litghost db785ed575
Merge pull request #945 from antmicro/loop_check_print_format 
int_loop_check.py: Fix output formatting
 2019-07-17 09:01:36 -07:00
litghost e334e7d4d2
Merge pull request #907 from antmicro/cfg_fuzzer 
Fuzzer for CFG_CENTER_MID tile
 2019-07-17 09:01:20 -07:00
Tim Ansell e32b9a3e27
Merge pull request #944 from SymbiFlow/dependabot/submodules/third_party/googletest-ee3aa83 
build(deps): bump third_party/googletest from `da10da0` to `ee3aa83`
 2019-07-15 09:37:02 -04:00
Tim Ansell dce952d62c
Merge pull request #943 from SymbiFlow/dependabot/submodules/third_party/abseil-cpp-44efe96 
build(deps): bump third_party/abseil-cpp from `0238ab0` to `44efe96`
 2019-07-15 09:36:34 -04:00
Tim Ansell 7b91571a21
Merge pull request #942 from SymbiFlow/dependabot/submodules/third_party/yosys-463f710 
build(deps): bump third_party/yosys from `d4f77d4` to `463f710`
 2019-07-15 09:35:03 -04:00
Tomasz Michalak d750e4fb43 int_loop_check.py: Fix output formatting 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-15 10:08:45 +02:00
dependabot-preview[bot] 4bcd4fd51a
build(deps): bump third_party/googletest from `da10da0` to `ee3aa83` 
Bumps [third_party/googletest](https://github.com/google/googletest) from `da10da0` to `ee3aa83`.
- [Release notes](https://github.com/google/googletest/releases)
- [Commits](da10da05c2...ee3aa83117)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
 2019-07-13 05:13:23 +00:00
dependabot-preview[bot] e74b4563bc
build(deps): bump third_party/abseil-cpp from `0238ab0` to `44efe96` 
Bumps [third_party/abseil-cpp](https://github.com/abseil/abseil-cpp) from `0238ab0` to `44efe96`.
- [Release notes](https://github.com/abseil/abseil-cpp/releases)
- [Commits](0238ab0a83...44efe96dfc)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
 2019-07-13 05:13:01 +00:00
dependabot-preview[bot] 7a23dce467
build(deps): bump third_party/yosys from `d4f77d4` to `463f710` 
Bumps [third_party/yosys](https://github.com/YosysHQ/yosys) from `d4f77d4` to `463f710`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](d4f77d408c...463f710066)

Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
 2019-07-13 05:12:41 +00:00
Tomasz Michalak f5ba30a81c 038-cfg: Add fuzzer for the CFG tile 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-13 07:10:18 +02:00
Tomasz Michalak e8fdac9f70 prjxray: Enable instance to be printed to file instead of stdout 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-11 15:54:47 +02:00
litghost 24d852c016
Merge pull request #941 from litghost/fixup_arty_harnes 
Fix D9/B8 in arty-swbut harness.
 2019-07-10 22:52:45 -07:00
Keith Rothman 3345f30817 Fix D9/B8 in arty-swbut harness. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-10 17:15:18 -07:00
litghost 36af12c149
Merge pull request #933 from antmicro/016-doutmux-amc31 
Fuzzer for DOUTMUX.MC31 and DFFMUX.MC31
 2019-07-10 15:47:33 -07:00
litghost 2d13b11f13
Merge pull request #935 from litghost/more_ilogic_bits 
Expand ILOGIC fuzzer to document additional ISERDES bits.
 2019-07-10 11:21:08 -07:00
Maciej Kurc b7fc6734d2 Ran format-py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:15:28 +02:00
Maciej Kurc 1e6b85b8a8 Increased number of specimens and CLBs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:07:11 +02:00
Maciej Kurc e08ce61fbe Modified 015 to include DFFMUX.MC31 for SLICEM 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:06:07 +02:00
Maciej Kurc 56cb76e90f Added a makefile which allows to fuzz features for both SLICEM and SLICEL but separate them during database merge. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 15:06:58 +02:00
litghost 05ef773e60
Merge pull request #938 from antmicro/mmcme2-base-addr-fix 
fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances
 2019-07-09 21:14:29 -07:00
litghost f400565f71
Merge pull request #926 from litghost/add_pll_interconnect_fuzzer 
Add PLL fuzzer
 2019-07-09 13:56:32 -07:00
Karol Gugala b989c2fc05 fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-09 18:42:04 +02:00
litghost 559f840097
Merge pull request #916 from antmicro/srl_minitests 
Minitests for SRLs
 2019-07-09 09:10:36 -07:00
Keith Rothman 280191ce0e Attempt to fix fuzzer error. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:16:45 -07:00
Keith Rothman 2a242bbd62 Expand ILOGIC fuzzer to document additional ISERDES bits. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:00:06 -07:00
Keith Rothman 444f214561 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 11:23:33 -07:00
Keith Rothman f92fb52576 Merge branch 'master' into add_pll_interconnect_fuzzer 2019-07-08 11:22:49 -07:00
Keith Rothman 3d1fade706 Change error output to stderr. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 11:21:43 -07:00
Maciej Kurc 67dba10fb7 Modified fuzzer 016 to include DOUTMUX.AMC31 feature. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-08 15:39:06 +02:00
Maciej Kurc 5c60639442 Added generation of sorted and "uniqued" FASM output 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-05 12:03:30 +02:00
Tomasz Michalak 948a3b21cc
Merge pull request #915 from antmicro/913_hclk_ioi_baseaddress 
Calculate base addresses for HCLK_IOI3 tiles.
 2019-07-04 23:32:20 +02:00
Keith Rothman b77c47b155 Fixes for zynq7 and PLL fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman a7f5a305b9 Add 034 to fuzzer makefile. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman 2728b781d1 Limit pips to the ones we care about. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman 30648d554a Complete initial PLL fuzzer. 
This solves for all unknown bits, but results in a large "IN_USE"
feature for apparently constant bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:58 -07:00
Keith Rothman bc822f8337 Update 032 with some fixes found during interconnect fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:58 -07:00
Keith Rothman 68ad409d23 Refactor PLL segbits to leverage known register file. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:53 -07:00
Karol Gugala 219f0f0175
Merge pull request #899 from antmicro/routing-bels 
Fuzzers: 007-timing: add routing BELs fuzzer
 2019-07-03 05:36:28 +02:00
Karol Gugala 78346781ce fuzzers: 007: fix Makefile targets definitions 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 19:04:10 +02:00
Maciej Kurc cbbf46112f Updated EDIF write to include cell attributes 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-02 16:03:02 +02:00
Karol Gugala 28d961a650 fuzzers: routing BELs: group timings by interconn oputput 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 13:08:14 +02:00
Tomasz Michalak e096d9c172 005-tilegrid: Add HCLK_IOI base addresses calculation 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-01 08:58:45 +02:00