e8eab9a45b
Bump chip database
2026-03-18 13:13:58 +01:00
6572d46414
Allowing the assignment of TDO pin (IO_S3_B3) on the second die for A2 ( #18 )
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* JTAG Pins also exist on 1B Die. Allow the S3 Bank to be assigned to the second Die
* Add attribute pins to class Bank, defining the list of allowed pins
* Potential fix for pull request finding
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
* Generate white list for WA Bank
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Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
2026-03-18 13:13:11 +01:00
bc3df10ff3
Add alternate clock routes and CP pass through [sc-184] ( #17 )
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* Add alternate clock routes
* Add pins for alternate signals
* Add more pips and placeholder for metadata
* Add data/mask for pips
* Add pips for testing
* fix CPE_CPLINES OUTx inputs
* resources
* Added rest of CP lines pips
* Change to block and resource
* Fix chip database error
* Timing data for CP lines
* Fix bitstream
* Bump database version
2026-02-25 08:11:36 +01:00
ba1eca17ca
fix C/P line errata caused by misunderstanding inversion
2026-01-09 13:45:33 +00:00
a2d62ae3af
cleanup
2025-12-30 10:12:10 +01:00
dfed52923a
mingw fixes
2025-12-30 10:08:50 +01:00
8f0b8a06f2
Extending for LUT permutation ( #14 )
2025-12-22 15:10:11 +01:00
81bb944e2b
Remove duplicated pips
2025-12-12 08:05:12 +01:00
5a43fa5fc0
fix C_CLKSEL/C_ENSEL input
2025-11-10 16:18:00 +00:00
1901f4b833
Bump chip database version
2025-11-10 12:00:22 +01:00
6f9f132d55
Make bridge pips not visible
2025-11-10 11:59:39 +01:00
632b223ce1
Add missing timings for IM
2025-11-10 11:59:31 +01:00
41d9fd80f4
update schematics to include switchboxes
2025-11-01 11:07:28 +00:00
7782c1c450
Merge pull request #13 from pu-cc/gatemate-fix-serdes-cdr
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TileBitDatabase: fix SERDES CDR parameters
2025-10-28 09:49:40 +01:00
d6a8239d55
TileBitDatabase: fix SERDES CDR parameters
2025-10-27 15:47:19 +01:00
fffdc6610c
Remove most of boost usage
2025-10-22 15:27:22 +02:00
e5df2fd309
add write_cmd_spll for designs without PLLs
2025-10-22 09:14:51 +02:00
1ab0612d22
Merge pull request #12 from pu-cc/bootaddr
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Secondary bitstream and scrubber features
2025-10-21 08:01:01 +02:00
4d60ba5d78
Merge branch 'YosysHQ:main' into bootaddr
2025-10-21 07:07:08 +02:00
8d1018796d
gmpack: reset config latches before bootaddr jump
2025-10-20 17:25:26 +02:00
ac547baf3b
gmpack: set `CMD_CHG_STATUS` config mode byte in bootaddr and background modes
2025-10-20 16:28:26 +02:00
9aa2711958
gmunpack: unpack `CMD_CFGRST` and `CMD_JUMP`
2025-10-20 13:58:12 +02:00
f081ba87cb
Bump version to 1.9
2025-10-17 11:56:29 +02:00
0283a03d82
gmpack: add background reconfiguration feature
2025-10-15 23:19:50 +02:00
f9183e4e2a
docs: update `CMD_CHG_STATUS` PLL control register bits
2025-10-15 19:40:40 +02:00
1f3f9aad85
gmpack: enable config clock for reconfiguration
2025-10-15 19:37:33 +02:00
05d8ef6a43
gmpack: revert `CFG_RECONFIG` and `CFG_CPE_CFG` separation
2025-10-15 17:35:20 +02:00
c74d0860d3
docs: update CMD_JUMP command
2025-10-15 17:24:56 +02:00
4597d1de96
gmpack: add bootaddr parameter for secondary bitstreams
2025-10-15 17:24:12 +02:00
72bc122449
gmpack: add option to clear config latches
2025-10-15 12:41:01 +02:00
5d37e3a18f
Add reconfig option
2025-10-07 13:43:51 +02:00
b4a3a82578
set stop and done only for die 0
2025-10-07 13:43:10 +02:00
867835f7bb
Better naming for D2D and pass trough TES as on hardware
2025-10-07 13:11:27 +02:00
781780f017
Fix TES and RES
2025-10-07 12:24:43 +02:00
89a4bd03d7
log iteration
2025-10-03 18:03:44 +02:00
14e478fca5
Fix multi die unpack
2025-10-02 16:03:30 +02:00
62bdd38fb0
Add delay blobs, fixes #9
2025-09-30 12:49:35 +02:00
0bbad32bc5
Merge pull request #11 from YosysHQ/pips
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Include and use connection timing data
2025-09-30 09:13:12 +02:00
36f6b5eec4
Bump version to 1.8
2025-09-23 08:08:07 +02:00
dda08d7bcd
Use proper timing info
2025-09-12 10:02:38 +02:00
8dfe05b5c5
put back old delay values
2025-09-11 16:45:42 +02:00
5bae9cae91
del_dummy is default delay
2025-09-11 15:21:09 +02:00
5a03c49c49
sortout multidie connections
2025-09-11 15:07:57 +02:00
81bb1c5cb8
additional wires for IO and CLK for SB_BIG/SML
2025-09-11 14:58:21 +02:00
3aec20a773
use sam delay
2025-09-11 14:11:47 +02:00
eae068fa3e
fix
2025-09-11 11:49:06 +02:00
d4f1bea09d
convert some connections to pips
2025-09-11 10:34:34 +02:00
fa0d53fe13
Merge pull request #10 from YosysHQ/bram2
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Cleanup BRAM
2025-09-05 08:37:19 +02:00
56c2bed294
Cleanup BRAM
2025-09-04 15:57:16 +02:00
c0d788ac6e
Merge pull request #7 from YosysHQ/bridge
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Add CPE bridge
2025-09-02 17:57:43 +02:00
Miodrag Milanovic
Hai Luong
Lofty
Patrick Urban