Lofty
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41d9fd80f4
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update schematics to include switchboxes
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2025-11-01 11:07:28 +00:00 |
Miodrag Milanović
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7782c1c450
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Merge pull request #13 from pu-cc/gatemate-fix-serdes-cdr
TileBitDatabase: fix SERDES CDR parameters
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2025-10-28 09:49:40 +01:00 |
Patrick Urban
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d6a8239d55
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TileBitDatabase: fix SERDES CDR parameters
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2025-10-27 15:47:19 +01:00 |
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Miodrag Milanovic
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fffdc6610c
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Remove most of boost usage
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2025-10-22 15:27:22 +02:00 |
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Miodrag Milanovic
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e5df2fd309
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add write_cmd_spll for designs without PLLs
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2025-10-22 09:14:51 +02:00 |
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Miodrag Milanović
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1ab0612d22
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Merge pull request #12 from pu-cc/bootaddr
Secondary bitstream and scrubber features
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2025-10-21 08:01:01 +02:00 |
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Patrick Urban
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4d60ba5d78
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Merge branch 'YosysHQ:main' into bootaddr
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2025-10-21 07:07:08 +02:00 |
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Patrick Urban
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8d1018796d
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gmpack: reset config latches before bootaddr jump
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2025-10-20 17:25:26 +02:00 |
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Patrick Urban
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ac547baf3b
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gmpack: set `CMD_CHG_STATUS` config mode byte in bootaddr and background modes
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2025-10-20 16:28:26 +02:00 |
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Patrick Urban
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9aa2711958
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gmunpack: unpack `CMD_CFGRST` and `CMD_JUMP`
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2025-10-20 13:58:12 +02:00 |
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Miodrag Milanovic
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f081ba87cb
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Bump version to 1.9
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2025-10-17 11:56:29 +02:00 |
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Patrick Urban
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0283a03d82
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gmpack: add background reconfiguration feature
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2025-10-15 23:19:50 +02:00 |
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Patrick Urban
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f9183e4e2a
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docs: update `CMD_CHG_STATUS` PLL control register bits
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2025-10-15 19:40:40 +02:00 |
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Patrick Urban
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1f3f9aad85
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gmpack: enable config clock for reconfiguration
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2025-10-15 19:37:33 +02:00 |
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Patrick Urban
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05d8ef6a43
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gmpack: revert `CFG_RECONFIG` and `CFG_CPE_CFG` separation
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2025-10-15 17:35:20 +02:00 |
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Patrick Urban
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c74d0860d3
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docs: update CMD_JUMP command
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2025-10-15 17:24:56 +02:00 |
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Patrick Urban
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4597d1de96
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gmpack: add bootaddr parameter for secondary bitstreams
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2025-10-15 17:24:12 +02:00 |
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Patrick Urban
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72bc122449
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gmpack: add option to clear config latches
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2025-10-15 12:41:01 +02:00 |
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Miodrag Milanovic
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5d37e3a18f
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Add reconfig option
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2025-10-07 13:43:51 +02:00 |
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Miodrag Milanovic
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b4a3a82578
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set stop and done only for die 0
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2025-10-07 13:43:10 +02:00 |
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Miodrag Milanovic
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867835f7bb
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Better naming for D2D and pass trough TES as on hardware
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2025-10-07 13:11:27 +02:00 |
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Miodrag Milanovic
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781780f017
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Fix TES and RES
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2025-10-07 12:24:43 +02:00 |
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Miodrag Milanovic
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89a4bd03d7
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log iteration
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2025-10-03 18:03:44 +02:00 |
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Miodrag Milanovic
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14e478fca5
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Fix multi die unpack
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2025-10-02 16:03:30 +02:00 |
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Miodrag Milanovic
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62bdd38fb0
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Add delay blobs, fixes #9
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2025-09-30 12:49:35 +02:00 |
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Miodrag Milanović
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0bbad32bc5
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Merge pull request #11 from YosysHQ/pips
Include and use connection timing data
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2025-09-30 09:13:12 +02:00 |
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Miodrag Milanovic
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36f6b5eec4
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Bump version to 1.8
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2025-09-23 08:08:07 +02:00 |
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Miodrag Milanovic
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dda08d7bcd
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Use proper timing info
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2025-09-12 10:02:38 +02:00 |
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Miodrag Milanovic
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8dfe05b5c5
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put back old delay values
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2025-09-11 16:45:42 +02:00 |
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Miodrag Milanovic
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5bae9cae91
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del_dummy is default delay
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2025-09-11 15:21:09 +02:00 |
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Miodrag Milanovic
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5a03c49c49
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sortout multidie connections
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2025-09-11 15:07:57 +02:00 |
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Miodrag Milanovic
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81bb1c5cb8
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additional wires for IO and CLK for SB_BIG/SML
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2025-09-11 14:58:21 +02:00 |
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Miodrag Milanovic
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3aec20a773
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use sam delay
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2025-09-11 14:11:47 +02:00 |
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Miodrag Milanovic
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eae068fa3e
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fix
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2025-09-11 11:49:06 +02:00 |
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Miodrag Milanovic
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d4f1bea09d
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convert some connections to pips
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2025-09-11 10:34:34 +02:00 |
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Miodrag Milanović
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fa0d53fe13
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Merge pull request #10 from YosysHQ/bram2
Cleanup BRAM
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2025-09-05 08:37:19 +02:00 |
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Miodrag Milanovic
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56c2bed294
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Cleanup BRAM
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2025-09-04 15:57:16 +02:00 |
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Miodrag Milanović
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c0d788ac6e
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Merge pull request #7 from YosysHQ/bridge
Add CPE bridge
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2025-09-02 17:57:43 +02:00 |
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Miodrag Milanovic
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f6654f83a7
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bump chipdb
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2025-09-02 14:04:37 +02:00 |
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Miodrag Milanovic
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0747679717
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Add bridge
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2025-09-02 08:07:43 +02:00 |
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Miodrag Milanović
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5d5f927d93
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Merge pull request #8 from YosysHQ/bram
Split BRAM into halfs
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2025-09-02 08:04:53 +02:00 |
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Miodrag Milanovic
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d04286b39a
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bump database version
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2025-08-29 14:57:41 +02:00 |
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Miodrag Milanovic
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b8c59f9f80
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Cleanup
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2025-08-29 14:47:59 +02:00 |
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Miodrag Milanovic
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74265fd1b8
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Split BRAMs into halfs
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2025-08-28 15:09:49 +02:00 |
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Miodrag Milanović
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22ec1e2d7b
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Merge pull request #6 from YosysHQ/new_timing
gatemate: add IOSEL as separate primitive
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2025-08-14 12:20:15 +02:00 |
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Miodrag Milanovic
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6ad315609d
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Bump database version
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2025-08-14 11:53:29 +02:00 |
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Miodrag Milanovic
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10b52f37f1
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Added IOSEL
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2025-08-13 15:49:44 +02:00 |
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Miodrag Milanovic
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0fb182de18
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rename to match port names
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2025-08-13 12:52:04 +02:00 |
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Miodrag Milanovic
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7d94d89855
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Fix direction
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2025-08-13 12:51:33 +02:00 |
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Lofty
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d7e7bf6e93
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update CPE schematics to cover C/P lines
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2025-07-19 11:35:43 +01:00 |