Lofty
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caa6f852cc
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further CPE schematic updates
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2025-07-15 21:44:18 +01:00 |
Miodrag Milanovic
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b6e7eda017
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Merge branch 'pu-cc-cfgmode'
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2025-07-09 12:52:31 +02:00 |
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Miodrag Milanovic
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542863a768
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Fix reading with gmunpack and clangformat
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2025-07-09 12:52:00 +02:00 |
Patrick Urban
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9148a1b81d
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Merge branch 'YosysHQ:main' into cfgmode
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2025-07-08 19:49:11 +02:00 |
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Patrick Urban
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0250f3e3f8
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Fix `CMD_CFGMODE` formatting
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2025-07-08 16:57:52 +02:00 |
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Patrick Urban
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a5ac25535d
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Add `CMD_CFGMODE` documentation
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2025-07-08 16:55:18 +02:00 |
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Patrick Urban
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10d7958f2e
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Disable crc bytes if set to "unused"
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2025-07-08 16:29:32 +02:00 |
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Patrick Urban
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2bb81624b1
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Fix crc error behaviour length byte
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2025-07-08 16:10:23 +02:00 |
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Lofty
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3c53e25071
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another CPE schematic update
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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c89ea91209
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Preps for MX8 support
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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a08f3ddba4
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Added few more connections
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2025-07-07 10:12:59 +02:00 |
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Lofty
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9f05921fc0
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update CPE schematic
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2025-07-07 10:12:59 +02:00 |
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Lofty
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c476c4f19c
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Render of CPE at the moment
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2025-07-07 10:12:59 +02:00 |
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Lofty
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b8f53da9a0
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WIP schematic for CPE
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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37e6d93a30
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Connect upper and lower L2T4
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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e7ca710859
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small change in model
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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d68f6fb08b
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Add CPE_COMP and CPE_CPLINES
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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6e63a05636
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Resolve name conflicts
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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2983a7f4ff
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Bump database version
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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78ac740eee
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Cleanup
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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aff4544421
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Cleanups
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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c27ceac7a0
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Added CPOUT and MUXOUT
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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4ba2a563a1
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Update primitives z locations
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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497e5cc2a1
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C_2D_IN flag
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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2bdf4065c0
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Add comb to seq connection
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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1a1a3488f7
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Improved model of CPE
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2025-07-07 10:12:59 +02:00 |
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Patrick Urban
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ebafe63481
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Enable crc error behaviour and spi io width selection in bitstream
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2025-07-03 17:02:47 +02:00 |
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Miodrag Milanovic
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ff2445f353
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Add D2D support
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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08b35c4538
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Add DDR pin information
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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2aa7ef65ba
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Add in tile position
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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a0afc3aea3
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Fixed wrong bank mapping
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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04a2dc2dc3
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Support reading multi die bitstreams
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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84c5734c9c
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clangformat
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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aacc795393
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Write proper multi die bitstream
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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58a098407b
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Bump version to 1.2
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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b5dda7196f
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Add PAD connections so we do not loose that info
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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dfc6458d5a
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Use _ as separator for PLL CFGs
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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83785af4ea
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GLBOUT and PLL fixes
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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f4ab570a39
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PLL fixes
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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bce9877556
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Create CLKIN and GLBOUT as primitives
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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8e3c659210
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Download only with delay files
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2025-06-05 07:00:12 +02:00 |
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Miodrag Milanovic
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5b9b1d013e
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Add timing modification delays
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2025-06-02 11:18:16 +02:00 |
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Miodrag Milanovic
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7800a49b4d
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Export database version
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2025-05-27 15:23:16 +02:00 |
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Miodrag Milanovic
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91eca20d10
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Add timing information from dly files
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2025-05-27 15:21:14 +02:00 |
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Miodrag Milanovic
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eb77def664
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Removed pins that can not be addressed
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2025-05-15 10:28:21 +02:00 |
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Miodrag Milanovic
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415de01bbe
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Extract SERDES config
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2025-04-30 09:57:28 +02:00 |
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Miodrag Milanovic
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69ed9f73ab
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Switch to standard type
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2025-04-28 17:38:40 +02:00 |
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Miodrag Milanovic
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adc3f7b133
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Support SERDES in bitstream
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2025-04-04 10:53:12 +02:00 |
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Miodrag Milanovic
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d79df6a1e0
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Fix due to documentation error
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2025-04-03 09:46:27 +02:00 |
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Miodrag Milanovic
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599b7a8c9c
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Store relative constraints in chipdb
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2025-04-02 13:53:34 +02:00 |