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alt_clk

alt_clk2

lut_perm

main

new_pip

ramio

#1

#10

#11

#12

#13

#14

#15

#15

#2

#3

#6

#7

#8

v0.1

v1.0

v1.1

v1.10

v1.11

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• 7f5f4801dd Timing data for CP lines alt_clk2 Miodrag Milanovic 2026-01-30 08:29:03 +0100
• 32d4237391 Fix chip database error Miodrag Milanovic 2026-01-22 13:52:36 +0100
• 908cad6b66 Change to block and resource Miodrag Milanovic 2026-01-22 12:24:32 +0100
• e1365a0c46 Added rest of CP lines pips Miodrag Milanovic 2026-01-20 08:32:40 +0100
• 5b0fb43451 resources Miodrag Milanovic 2026-01-19 15:10:17 +0100
• 4587c877d3
  Merge 79c4696f54 into ba1eca17ca Miodrag Milanović 2026-01-15 04:21:42 +0530
• 79c4696f54 fix CPE_CPLINES OUTx inputs alt_clk Miodrag Milanovic 2026-01-14 11:37:22 +0100
• ba1eca17ca fix C/P line errata caused by misunderstanding inversion main v1.11 Lofty 2026-01-09 13:45:33 +0000
• f7b4f7e719 Add pips for testing Miodrag Milanovic 2026-01-09 14:17:28 +0100
• 52bf317d24 Add data/mask for pips Miodrag Milanovic 2026-01-08 16:55:50 +0100
• f82186b2a7 Add more pips and placeholder for metadata Miodrag Milanovic 2026-01-08 16:04:07 +0100
• a2d62ae3af cleanup Miodrag Milanovic 2025-12-30 10:12:10 +0100
• dfed52923a mingw fixes Miodrag Milanovic 2025-12-30 10:08:50 +0100
• 30b4878fb0 Add pins for alternate signals Miodrag Milanovic 2025-12-24 11:16:34 +0100
• 2590f03408 Add alternate clock routes Miodrag Milanovic 2025-12-24 10:43:57 +0100
• 8f0b8a06f2
  Extending for LUT permutation (#14) Miodrag Milanović 2025-12-22 15:10:11 +0100
• a8d58a28a6 Support CP lines for lut inputs Miodrag Milanovic 2025-12-18 14:58:19 +0100
• 0c75c2e799 Cleanup and bump version Miodrag Milanovic 2025-12-18 10:05:37 +0100
• 76327c64b3 Need default connections Miodrag Milanovic 2025-12-18 10:00:16 +0100
• ed5f85b371 wip new_pip Miodrag Milanovic 2025-12-17 08:32:34 +0100
• 443f249b84 disable these for now Miodrag Milanovic 2025-12-15 09:16:17 +0100
• a23d438ac4 fix pips Miodrag Milanovic 2025-12-11 18:35:30 +0100
• ab505c765d Fix wrong name and select proper timing Miodrag Milanovic 2025-12-08 15:14:55 +0100
• b878741e28 Enable clock CP lines Miodrag Milanovic 2025-12-05 10:14:46 +0100
• 6495c1f1bc do not use CP lines for now Miodrag Milanovic 2025-12-04 14:09:44 +0100
• 6d633ea23b need to use _int Miodrag Milanovic 2025-12-04 13:25:06 +0100
• 3d2699ffbf Enable pins Miodrag Milanovic 2025-12-04 09:27:10 +0100
• 014a237783 wip Miodrag Milanovic 2025-12-04 08:01:22 +0100
• 24aace0b30 wip Miodrag Milanovic 2025-12-03 14:24:56 +0100
• c529ceec32 wip Miodrag Milanovic 2025-12-01 11:02:56 +0100
• 718b8e7766 wip Miodrag Milanovic 2025-11-26 13:51:09 +0100
• 81bb944e2b Remove duplicated pips Miodrag Milanovic 2025-12-12 08:05:12 +0100
• 1756e70913 limit left edge ramio Miodrag Milanovic 2025-11-24 08:20:44 +0100
• 804e8dd508 wip Miodrag Milanovic 2025-11-21 13:39:10 +0100
• 5a43fa5fc0 fix C_CLKSEL/C_ENSEL input Lofty 2025-11-10 16:17:52 +0000
• 1901f4b833 Bump chip database version v1.10 Miodrag Milanovic 2025-11-10 12:00:22 +0100
• 6f9f132d55 Make bridge pips not visible Miodrag Milanovic 2025-10-29 08:26:35 +0100
• 632b223ce1 Add missing timings for IM Miodrag Milanovic 2025-10-29 08:25:26 +0100
• 41d9fd80f4 update schematics to include switchboxes Lofty 2025-11-01 11:07:22 +0000
• ee22e55482 Make bridge pips not visible lut_perm Miodrag Milanovic 2025-10-29 08:26:35 +0100
• 03e4fa295d Add LUT permutation pips Miodrag Milanovic 2025-10-29 08:26:10 +0100
• cfcb90dce2 Add missing timings for IM Miodrag Milanovic 2025-10-29 08:25:26 +0100
• 7782c1c450
  Merge pull request #13 from pu-cc/gatemate-fix-serdes-cdr Miodrag Milanović 2025-10-28 09:49:40 +0100
• d6a8239d55 TileBitDatabase: fix SERDES CDR parameters Patrick Urban 2025-10-27 15:47:19 +0100
• fffdc6610c Remove most of boost usage Miodrag Milanovic 2025-10-22 15:27:22 +0200
• e5df2fd309 add write_cmd_spll for designs without PLLs Miodrag Milanovic 2025-10-22 09:14:51 +0200
• 1ab0612d22
  Merge pull request #12 from pu-cc/bootaddr Miodrag Milanović 2025-10-21 08:01:01 +0200
• 4d60ba5d78
  Merge branch 'YosysHQ:main' into bootaddr Patrick Urban 2025-10-21 07:07:08 +0200
• 8d1018796d gmpack: reset config latches before bootaddr jump Patrick Urban 2025-10-20 17:25:26 +0200
• ac547baf3b gmpack: set `CMD_CHG_STATUS` config mode byte in bootaddr and background modes Patrick Urban 2025-10-20 16:28:26 +0200
• 9aa2711958 gmunpack: unpack `CMD_CFGRST` and `CMD_JUMP` Patrick Urban 2025-10-20 13:58:12 +0200
• f081ba87cb Bump version to 1.9 v1.9 Miodrag Milanovic 2025-10-17 11:56:29 +0200
• 0283a03d82 gmpack: add background reconfiguration feature Patrick Urban 2025-10-15 23:19:50 +0200
• f9183e4e2a docs: update `CMD_CHG_STATUS` PLL control register bits Patrick Urban 2025-10-15 19:40:40 +0200
• 1f3f9aad85 gmpack: enable config clock for reconfiguration Patrick Urban 2025-10-15 19:37:33 +0200
• 05d8ef6a43 gmpack: revert `CFG_RECONFIG` and `CFG_CPE_CFG` separation Patrick Urban 2025-10-15 17:35:20 +0200
• c74d0860d3 docs: update CMD_JUMP command Patrick Urban 2025-10-15 17:24:56 +0200
• 4597d1de96 gmpack: add bootaddr parameter for secondary bitstreams Patrick Urban 2025-10-15 17:24:12 +0200
• 72bc122449 gmpack: add option to clear config latches Patrick Urban 2025-10-15 12:41:01 +0200
• 5d37e3a18f Add reconfig option Miodrag Milanovic 2025-10-07 13:43:51 +0200
• b4a3a82578 set stop and done only for die 0 Miodrag Milanovic 2025-10-07 13:43:10 +0200
• 867835f7bb Better naming for D2D and pass trough TES as on hardware Miodrag Milanovic 2025-10-07 13:11:27 +0200
• 781780f017 Fix TES and RES Miodrag Milanovic 2025-10-07 12:24:43 +0200
• 89a4bd03d7 log iteration Miodrag Milanovic 2025-10-03 18:03:44 +0200
• 14e478fca5 Fix multi die unpack Miodrag Milanovic 2025-10-02 16:03:30 +0200
• 62bdd38fb0 Add delay blobs, fixes #9 v1.8 Miodrag Milanovic 2025-09-30 12:49:35 +0200
• 0bbad32bc5
  Merge pull request #11 from YosysHQ/pips Miodrag Milanović 2025-09-30 09:13:12 +0200
• 36f6b5eec4 Bump version to 1.8 Miodrag Milanovic 2025-09-23 08:08:07 +0200
• dda08d7bcd Use proper timing info Miodrag Milanovic 2025-09-12 10:02:38 +0200
• 8dfe05b5c5 put back old delay values Miodrag Milanovic 2025-09-11 16:45:42 +0200
• 5bae9cae91 del_dummy is default delay Miodrag Milanovic 2025-09-11 15:21:09 +0200
• 5a03c49c49 sortout multidie connections Miodrag Milanovic 2025-09-11 15:07:57 +0200
• 81bb1c5cb8 additional wires for IO and CLK for SB_BIG/SML Miodrag Milanovic 2025-09-11 14:58:21 +0200
• 3aec20a773 use sam delay Miodrag Milanovic 2025-09-11 14:11:47 +0200
• eae068fa3e fix Miodrag Milanovic 2025-09-11 11:49:06 +0200
• d4f1bea09d convert some connections to pips Miodrag Milanovic 2025-09-11 10:34:34 +0200
• fa0d53fe13
  Merge pull request #10 from YosysHQ/bram2 v1.7 Miodrag Milanović 2025-09-05 08:37:19 +0200
• 56c2bed294 Cleanup BRAM Miodrag Milanovic 2025-09-04 15:57:16 +0200
• c0d788ac6e
  Merge pull request #7 from YosysHQ/bridge v1.6 Miodrag Milanović 2025-09-02 17:57:43 +0200
• f6654f83a7 bump chipdb Miodrag Milanovic 2025-09-02 14:04:37 +0200
• 0747679717 Add bridge Miodrag Milanovic 2025-08-19 09:07:21 +0200
• 5d5f927d93
  Merge pull request #8 from YosysHQ/bram v1.5 Miodrag Milanović 2025-09-02 08:04:53 +0200
• d04286b39a bump database version Miodrag Milanovic 2025-08-29 14:57:41 +0200
• b8c59f9f80 Cleanup Miodrag Milanovic 2025-08-29 14:47:59 +0200
• 74265fd1b8 Split BRAMs into halfs Miodrag Milanovic 2025-08-28 15:09:49 +0200
• 22ec1e2d7b
  Merge pull request #6 from YosysHQ/new_timing v1.4 Miodrag Milanović 2025-08-14 12:20:15 +0200
• 6ad315609d Bump database version Miodrag Milanovic 2025-08-14 11:53:29 +0200
• 10b52f37f1 Added IOSEL Miodrag Milanovic 2025-08-13 15:49:44 +0200
• 0fb182de18 rename to match port names Miodrag Milanovic 2025-08-13 12:52:04 +0200
• 7d94d89855 Fix direction Miodrag Milanovic 2025-08-13 12:51:33 +0200
• d7e7bf6e93 update CPE schematics to cover C/P lines Lofty 2025-07-19 11:35:43 +0100
• caa6f852cc further CPE schematic updates Lofty 2025-07-15 21:44:18 +0100
• b6e7eda017 Merge branch 'pu-cc-cfgmode' Miodrag Milanovic 2025-07-09 12:52:31 +0200
• 542863a768 Fix reading with gmunpack and clangformat Miodrag Milanovic 2025-07-09 12:52:00 +0200
• 9148a1b81d
  Merge branch 'YosysHQ:main' into cfgmode Patrick Urban 2025-07-08 19:49:11 +0200
• 0250f3e3f8 Fix `CMD_CFGMODE` formatting Patrick Urban 2025-07-08 16:57:52 +0200
• a5ac25535d Add `CMD_CFGMODE` documentation Patrick Urban 2025-07-08 16:55:18 +0200
• 10d7958f2e Disable crc bytes if set to "unused" Patrick Urban 2025-07-08 16:29:32 +0200
• 2bb81624b1 Fix crc error behaviour length byte Patrick Urban 2025-07-08 16:10:23 +0200
• 3c53e25071 another CPE schematic update v1.3 Lofty 2025-07-07 09:07:01 +0100