Miodrag Milanovic
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eb77def664
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Removed pins that can not be addressed
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2025-05-15 10:28:21 +02:00 |
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Miodrag Milanovic
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415de01bbe
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Extract SERDES config
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2025-04-30 09:57:28 +02:00 |
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Miodrag Milanovic
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69ed9f73ab
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Switch to standard type
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2025-04-28 17:38:40 +02:00 |
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Miodrag Milanovic
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adc3f7b133
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Support SERDES in bitstream
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2025-04-04 10:53:12 +02:00 |
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Miodrag Milanovic
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d79df6a1e0
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Fix due to documentation error
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2025-04-03 09:46:27 +02:00 |
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Miodrag Milanovic
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599b7a8c9c
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Store relative constraints in chipdb
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2025-04-02 13:53:34 +02:00 |
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Miodrag Milanovic
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7288755e01
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Fix direction
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2025-03-22 14:12:09 +01:00 |
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Miodrag Milanovic
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9ccc8588c0
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RAM configuration bits
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2025-03-21 10:01:41 +01:00 |
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Miodrag Milanovic
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dd3591cfa9
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Group RAM data 40 bytes per row
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2025-03-20 12:50:18 +01:00 |
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Miodrag Milanovic
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2645240bf9
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Add flags for clock source
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2025-03-18 09:20:12 +01:00 |
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Miodrag Milanovic
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74197786e5
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Export pad bank information
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2025-03-13 12:12:40 +01:00 |
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Miodrag Milanovic
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d9313105b4
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Remove some virtual pins
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2025-03-11 15:52:39 +01:00 |
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Miodrag Milanovic
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6bcef60680
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Remove GPIO reset signal
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2025-03-10 11:16:15 +01:00 |
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Miodrag Milanovic
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d814a80c66
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Fixed PLL wires
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2025-03-10 09:49:28 +01:00 |
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Miodrag Milanovic
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8e0cb69fd7
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Off by one PLL config creating error
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2025-03-07 09:57:56 +01:00 |
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Miodrag Milanovic
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f7491ee70d
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Update SERDES pin names
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2025-03-07 09:17:15 +01:00 |
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Miodrag Milanovic
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b8d2d4a45a
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Update DDR_I for S1-3
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2025-03-07 09:05:48 +01:00 |
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Miodrag Milanovic
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405cda1585
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Added CFG_CTRL
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2025-03-04 14:58:54 +01:00 |
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Miodrag Milanovic
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cd9c9b3e3b
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Added serdes and use real ram port names
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2025-03-04 13:10:40 +01:00 |
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Miodrag Milanovic
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4a2de30408
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Add missing GPIO clock signals
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2025-03-04 11:31:40 +01:00 |
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Miodrag Milanovic
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e0dc4ed695
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Added RAM block connections
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2025-03-04 10:53:08 +01:00 |
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Miodrag Milanovic
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7bb1399132
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add alternate CPE inputs
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2025-02-24 08:18:58 +01:00 |
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Miodrag Milanovic
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fca45fce23
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Model CPE as two halfs
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2025-02-18 14:09:46 +01:00 |
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Miodrag Milanovic
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017722609d
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Add DDR connections
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2025-02-06 08:56:32 +01:00 |
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Miodrag Milanovic
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af81ad935b
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edge case fix
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2025-02-05 14:49:00 +01:00 |
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Miodrag Milanovic
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ef07eb080e
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tool to extract constids.inc
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2025-02-05 13:34:07 +01:00 |
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Miodrag Milanovic
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1e60c0f6fb
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Properly named configuration bits
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2025-02-05 12:38:27 +01:00 |
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Miodrag Milanovic
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14b21aa4c7
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Properly named configuration bits
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2025-02-05 12:28:31 +01:00 |
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Miodrag Milanovic
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e3414fde27
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Enable reverse lookup rom RAM_I1/2 inputs
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2025-02-05 10:21:16 +01:00 |
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Miodrag Milanovic
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cbceacc09f
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Connect feedback pin
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2025-02-04 11:18:21 +01:00 |
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Miodrag Milanovic
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16fddfa1a1
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Fix off-by-one typo
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2025-02-04 10:13:32 +01:00 |
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Miodrag Milanovic
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c40e44027d
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Update naming and document unused bits
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2025-02-04 10:12:42 +01:00 |
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Miodrag Milanovic
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0dde71212c
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Implement SB_DRIVE support
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2025-02-03 11:50:33 +01:00 |
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Miodrag Milanovic
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a31f1d7d7d
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Disable some routes until we better handle CPE routing
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2025-01-27 13:17:01 +01:00 |
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Miodrag Milanovic
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fe94f5dc20
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Fix multi die chipdb creation
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2025-01-24 11:58:58 +01:00 |
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Miodrag Milanovic
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c62215338f
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Expose extra tile information
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2025-01-23 12:52:36 +01:00 |
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Miodrag Milanovic
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033532d5d0
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Added muxes for LES,BES,RES and TES
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2025-01-22 13:28:34 +01:00 |
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Miodrag Milanovic
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1d93989ed5
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Add bit mapping for edges
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2025-01-22 12:19:41 +01:00 |
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Miodrag Milanovic
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dce582deb4
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cleanup
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2025-01-20 09:27:17 +01:00 |
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Miodrag Milanovic
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e50e737f1b
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Add USR_RSTN
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2025-01-20 08:40:45 +01:00 |
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Miodrag Milanovic
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6c771b5ac9
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Add edge select blocks connections
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2025-01-20 08:36:02 +01:00 |
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Miodrag Milanovic
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ddcf3b1143
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fix typo
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2025-01-18 13:23:04 +01:00 |
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Miodrag Milanovic
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a0b7f0bcbe
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Cleaner way to get global mesh
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2025-01-17 13:21:25 +01:00 |
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Miodrag Milanovic
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2b2d7a6ad9
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Map pll pins to glbout connections
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2025-01-16 14:57:33 +01:00 |
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Miodrag Milanovic
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d2aaea4adb
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Made data classes able to be ordered
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2025-01-14 15:15:40 +01:00 |
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Miodrag Milanovic
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cf84095539
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Fixed typo
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2025-01-13 18:32:07 +01:00 |
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Miodrag Milanovic
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d38dc266d6
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Global clock fixes, disable SB_DRIVE for now
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2025-01-13 13:16:06 +01:00 |
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Miodrag Milanovic
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f6f887ccfe
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Fix SB_DRIVE index
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2025-01-13 13:14:53 +01:00 |
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Miodrag Milanovic
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07d7827cd4
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Fix exporting CLKIN and GLBOUT settings
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2025-01-13 13:14:13 +01:00 |
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Miodrag Milanovic
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d1df911fca
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Some more global/pll routing
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2025-01-06 14:13:49 +01:00 |