Rod Whitby
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18a24c65ea
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Add spiOverJtag support for Xilinx xc7k325tffg676 part.
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2022-02-19 13:14:50 +10:30 |
Gwenhael Goavec-Merou
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951c4f0f51
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Merge pull request #176 from hansemro/zybo_z7
Add digilent_zybo_z7 10/20 support
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2022-02-16 07:23:03 +01:00 |
Hansem Ro
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905e96dfec
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Add digilent_zybo_z7 10/20 support
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2022-02-15 21:01:11 -08:00 |
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Gwenhael Goavec-Merou
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5099b57ce3
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Merge pull request #174 from tarikgraba/master
Add support for Terasic DE1-SoC board
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2022-02-09 20:14:38 +01:00 |
TG
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94ca103360
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doc: add reference to the Terasic DE1-SoC board
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2022-02-09 18:40:16 +01:00 |
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TG
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89e1fb89d2
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doc: add Cyclone V SE SoC FPGA to the supported parts
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2022-02-09 18:40:16 +01:00 |
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Gwenhael Goavec-Merou
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56457a4023
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Merge pull request #173 from rstephan/tables
Nicer layout for the boards/fpga/cables table
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2022-02-09 18:17:35 +01:00 |
Stephan Ruloff
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63c9ec01b7
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Fixed right alignment problem.
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2022-02-09 17:55:16 +01:00 |
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TG
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5aa34c6364
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board: add Terasic DE1-SoC board
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2022-02-09 17:22:38 +01:00 |
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TG
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d188314ae3
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part: add altera 5CSEMA5 (cyclone V Soc)
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2022-02-09 17:21:19 +01:00 |
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Gwenhael Goavec-Merou
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a0ef85d516
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display: use a less dark blue
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2022-02-09 08:33:21 +01:00 |
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Gwenhael Goavec-Merou
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687503673e
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jtag: for unknown IDCODE display a more complete error
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2022-02-09 08:32:41 +01:00 |
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Gwenhael Goavec-Merou
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0a43d1b797
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part: add map manufacturer id <-> name
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2022-02-09 08:32:06 +01:00 |
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Stephan Ruloff
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12c5e6ba19
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Nicer layout for the boards/fpga/cables table
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2022-02-08 19:31:37 +01:00 |
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Gwenhael Goavec-Merou
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498c01889f
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spiFlash: fix overflow test (#172)
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2022-02-07 07:44:11 +01:00 |
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Gwenhael Goavec-Merou
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68b26106d0
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Merge pull request #171 from chiplet/master
board: add tangnano1k
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2022-01-29 20:41:26 +01:00 |
Verneri Hirvonen
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a385719765
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doc: tangnano1k doesn't have external flash
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2022-01-29 17:50:45 +02:00 |
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Verneri Hirvonen
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350570ad2d
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board: add tangnano1k to board_list
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2022-01-28 13:53:33 +02:00 |
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Gwenhael Goavec-Merou
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eaa01ca9bb
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Merge pull request #170 from DaveBerkeley/master
add device xc6slx16csg324
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2022-01-28 08:38:33 +01:00 |
Dave Berkeley
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ed4d8398ac
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added spiOverJtag_xc6slx16csg324.bit.gz
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2022-01-28 07:18:44 +00:00 |
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Verneri Hirvonen
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a133be582d
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board: add tangnano1k
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2022-01-27 23:10:20 +02:00 |
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Verneri Hirvonen
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977900954e
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part: add GW1NZ-1
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2022-01-27 22:55:21 +02:00 |
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Gwenhael Goavec-Merou
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1a51f7b7f0
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Merge pull request #168 from Martoni/master
Adding two Xilinx development kit AC701 (artix7) and ZC702 (zynq)
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2022-01-27 18:52:03 +01:00 |
Fabien Marteau
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dc5eedfdde
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adding constraints AC701
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2022-01-27 09:32:59 +01:00 |
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Dave Berkeley
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11a85eb19d
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added spi flash support for xc6slx16csg324
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2022-01-27 08:19:55 +00:00 |
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Fabien Marteau
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db407a4263
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adding xilinx AC701 development kit
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2022-01-26 16:42:03 +01:00 |
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Fabien Marteau
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f30cca46d8
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no dash for zedboard fpga name
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2022-01-26 16:29:35 +01:00 |
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Fabien Marteau
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99df282905
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alphabetical order
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2022-01-26 16:27:16 +01:00 |
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Fabien Marteau
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0d1905425c
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add board zc702 in board.hpp
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2022-01-26 16:21:52 +01:00 |
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Fabien Marteau
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ed390f468a
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Adding dev kit Xilinx Zynq-7000 SoC ZC702 Evaluation Kit
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2022-01-26 16:14:00 +01:00 |
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Gwenhael Goavec-Merou
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b4ffe4bf66
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xilinx: fix typo
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2022-01-24 18:58:32 +01:00 |
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Gwenhael Goavec-Merou
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b91cd00688
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doc/boards: tang Nano s/4k/9k/g
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2022-01-22 16:01:16 +01:00 |
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Gwenhael Goavec-Merou
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f87686fb48
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Merge pull request #166 from Icenowy/gw1nr-9c
Add support for Gowin GW1NR-9C
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2022-01-22 16:00:20 +01:00 |
Icenowy Zheng
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acf677dd46
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tangnano9k: new board, with the same cable w/ tangnano4k
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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2022-01-22 20:51:05 +08:00 |
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Icenowy Zheng
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dc4a454b94
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gowin: add support for GW1NR-9C
GW1NR-9C has a different idcode with GW1NR-9.
Add support for it by adding the idcode.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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2022-01-22 20:49:35 +08:00 |
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Gwenhael Goavec-Merou
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fb2aadadad
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cable: adding Olimex ARM-USB-OCD-H
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2022-01-20 19:37:50 +01:00 |
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Gwenhael Goavec-Merou
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a90ac3db7b
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doc/boards: complete contraints
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2022-01-19 18:59:24 +01:00 |
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Gwenhael Goavec-Merou
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2d4c634b80
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doc/FPGAs: ice40 memory support
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2022-01-19 18:59:02 +01:00 |
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Gwenhael Goavec-Merou
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1ab454359f
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ftdiJtagMPSSE,ftdipp_mpsse: fix verbose level -> must be an int8_t not uint8_t
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2022-01-19 18:42:15 +01:00 |
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Gwenhael Goavec-Merou
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5f35867f23
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Merge pull request #163 from umarcor/doc-fpgas
doc: declare FPGA compatibility list through YAML file
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2022-01-18 08:45:44 +01:00 |
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Gwenhael Goavec-Merou
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5365a9f9cf
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ice40: program_cram, add TN ref
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2022-01-18 08:37:07 +01:00 |
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Gwenhael Goavec-Merou
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eb462d2bec
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main: bitstream default target depends on mode spi/jtag
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2022-01-18 08:09:54 +01:00 |
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Gwenhael Goavec-Merou
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60ba2b1ccc
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ice40: add CRAM support
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2022-01-18 08:08:48 +01:00 |
umarcor
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70d17f2cc5
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doc: cross-reference FPGA compatibility table and vendor notes
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2022-01-17 23:28:18 +01:00 |
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umarcor
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7fcc9b7d2c
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doc: declare FPGA compatibility list through YAML file
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2022-01-17 23:21:23 +01:00 |
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Gwenhael Goavec-Merou
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6597dcf374
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spiOverJtag: add bitstream for spartan6 LX16 FTG256
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2022-01-15 11:47:15 +01:00 |
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Gwenhael Goavec-Merou
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1d94270eaf
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spiOverJtag: spartan6 FTG 256 ucf
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2022-01-15 11:47:15 +01:00 |
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Gwenhael Goavec-Merou
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46219bd495
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Merge pull request #162 from antmicro/k160t
part: add Kintex 160T
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2022-01-14 09:08:56 +01:00 |
Karol Gugala
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dbc6551a3c
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part: add Kintex 160T
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
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2022-01-14 09:01:23 +01:00 |
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Gwenhael Goavec-Merou
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ecc76baa97
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board: alinx AXU2CGA
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2022-01-13 08:55:26 +01:00 |