doc: declare FPGA compatibility list through YAML file
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umarcor
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@ -43,3 +43,4 @@ build/
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/doc/_build/
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/doc/_theme/
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/doc/compatibility/boards.inc
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/doc/compatibility/fpga.inc
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@ -0,0 +1,234 @@
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Anlogic:
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- Description: EG4
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Model: S20
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URL: http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3
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Memory: OK
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Flash: AS
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- Description: SALELF 2
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Model: EF2M45
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URL: http://www.anlogic.com/prod_view.aspx?TypeId=12&Id=170&FId=t3:12:3
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Memory: OK
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Flash: OK
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Cologne Chip:
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- Description: GateMate Series
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Model:
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- CCGM1A1
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- CCGM1A2
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- CCGM1A4
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- CCGM1A9
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- CCGM1A16
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- CCGM1A25
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URL: https://colognechip.com/programmable-logic/gatemate/
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Memory: OK
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Flash: OK
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Efinix:
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- Description: Trion
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Model: T8
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URL: https://www.efinixinc.com/products-trion.html
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Memory: NA
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Flash: OK
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- Description: Titanium
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Model: Ti60
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URL: https://www.efinixinc.com/products-titanium.html
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Memory: NA
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Flash: OK
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Gowin:
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- Description: GW1N
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Model:
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- GW1N-1
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- GW1N-4
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- GW1NR-9
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- GW1NS-2C
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- GW1NSR-4C
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URL: https://www.gowinsemi.com/en/product/detail/2/
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Memory: OK
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Flash: IF
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Intel:
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- Description: Cyclone III
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Model: EP3C16
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URL: https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html
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Memory: OK
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Flash: OK
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- Description: Cyclone IV CE
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Model: EP4CE22
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URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html
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Memory: OK
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Flash: OK
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- Description: Cyclone V E
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Model:
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- 5CEA2
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- 5CEBA4
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URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html
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Memory: OK
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Flash: OK
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- Description: Cyclone 10 LP
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Model: 10CL025
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URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html
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Memory: OK
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Flash: OK
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Lattice:
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- Description: CrossLink-NX
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Model: LIFCL-40
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URL: https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX
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Memory: OK
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Flash: OK
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- Description: ECP5
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Model:
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- 25F
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- 5G 85F
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URL: http://www.latticesemi.com/Products/FPGAandCPLD/ECP5
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Memory: OK
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Flash: OK
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- Description: iCE40
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Model:
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- HX1K
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- HX4K
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- HX8K
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- UP5K
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URL: https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40
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Memory: NA
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Flash: AS
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- Description: MachXO2
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Model:
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- '256'
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- '640'
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- '640U'
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- '1200'
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- '1200U'
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- '2000'
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- '2000U'
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- '4000'
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- '7000'
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URL: https://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO2
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Memory: OK
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Flash: OK
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- Description: MachXO3D
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Model:
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- '4300'
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- '9400'
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URL: http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3D.aspx
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Memory: OK
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Flash: OK
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- Description: MachXO3LF
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Model:
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- '640'
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- '1300'
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- '2100'
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- '4300'
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- '6900'
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- '9400'
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URL: http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3.aspx
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Memory: OK
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Flash: OK
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Xilinx:
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- Description: Artix 7
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Model:
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- xc7a35ti
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- xc7a50t
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- xc7a75t
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- xc7a100t
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- xc7a200t
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URL: https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html
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Memory: OK
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Flash: OK
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- Description: Kintex 7
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Model:
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- xc7k160t
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- xc7k325t
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URL: https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable
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Memory: OK
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Flash: NT
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- Description: Spartan 3
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Model: xc3s200
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URL: https://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html
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Memory: OK
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Flash: NA
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- Description: Spartan 6
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Model:
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- xc6slx9
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- xc6slx16
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- xc6slx25
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- xc6slx45
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URL: https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html
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Memory: OK
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Flash: OK
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- Description: Spartan 7
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Model:
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- xc7s15
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- xc7s25
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- xc7s50
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URL: https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html
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Memory: OK
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Flash: OK
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- Description: XC9500XL
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Model:
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- xc9536xl
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- xc9572xl
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- xc95144xl
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- xc95188xl
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URL: https://www.xilinx.com/support/documentation/data_sheets/ds054.pdf
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Memory: NA
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Flash: OK
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- Description: XC2C (coolrunner II)
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Model: xc2c32a
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URL: https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf
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Memory: TBD
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Flash: OK
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- Description: XCF
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Model:
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- xcf01s
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- xcf02s
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- xcf04s
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URL: https://www.xilinx.com/products/silicon-devices/configuration-memory/platform-flash.html
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Memory: NA
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Flash: OK
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- Description: Zynq7000
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Model:
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- xc7z010
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- xc7z020
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URL: https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html
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Memory: OK
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Flash: NA
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- Description: ZynqMPSoC
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Model: xczu2cg
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URL: https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html
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Memory: OK
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Flash: NA
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@ -3,36 +3,7 @@
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FPGAs
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#####
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============= =================================================================================================================================== ====== =====
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Vendor Model Memory Flash
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============= =================================================================================================================================== ====== =====
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Anlogic `EG4S20 <http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168&FId=t3:10:3>`__ OK AS
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Anlogic `EF2M45 <http://www.anlogic.com/prod_view.aspx?TypeId=12&Id=170&FId=t3:12:3>`__ OK OK
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Cologne Chip `GateMate Series <https://colognechip.com/programmable-logic/gatemate/>`__ OK OK
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Efinix `Trion T8 <https://www.efinixinc.com/products-trion.html>`__ NA OK
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Efinix `Titanium Ti60 <https://www.efinixinc.com/products-titanium.html>`__ NA OK
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Gowin `GW1N (GW1N-1, GW1N-4, GW1NR-9, GW1NS-2C, GW1NSR-4C) <https://www.gowinsemi.com/en/product/detail/2/>`__ OK IF
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Intel Cyclone III `EP3C16 <https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-iii/support.html>`__ OK OK
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Intel Cyclone IV CE `EP4CE22 <https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iv/features.html>`__ OK OK
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Intel Cyclone V E `5CEA2, 5CEBA4 <https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html>`__ OK OK
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Intel Cyclone 10 LP `10CL025 <https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html>`__ OK OK
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Lattice `CrossLink-NX (LIFCL-40) <https://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLink-NX>`__ OK OK
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Lattice `ECP5 (25F, 5G 85F) <http://www.latticesemi.com/Products/FPGAandCPLD/ECP5>`__ OK OK
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Lattice `iCE40 (HX1K, HX4K, HX8K, UP5K) <https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40>`__ NA AS
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Lattice `MachXO2 <https://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO2>`__ OK OK
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Lattice `MachXO3D <http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3D.aspx>`__ OK OK
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Lattice `MachXO3LF <http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3.aspx>`__ OK OK
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Xilinx Artix 7 `xc7a35ti, xc7a50t, xc7a75t, xc7a100t, xc7a200t <https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html>`__ OK OK
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Xilinx Kintex 7 `xc7k160t, xc7k325t <https://www.xilinx.com/products/silicon-devices/fpga/kintex-7.html#productTable>`__ OK NT
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Xilinx Spartan 3 `xc3s200 <https://www.xilinx.com/products/silicon-devices/fpga/spartan-3.html>`__ OK NA
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Xilinx Spartan 6 `xc6slx9, xc6slx16, xc6slx25, xc6slx45 <https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html>`__ OK OK
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Xilinx Spartan 7 `xc7s15, xc7s25, xc7s50 <https://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html>`__ OK OK
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Xilinx XC9500XL `xc9536xl, xc9572xl, xc95144xl, xc95188xl <https://www.xilinx.com/support/documentation/data_sheets/ds054.pdf>`__ NA OK
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Xilinx XC2C (coolrunner II) `xc2c32a <https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf>`__ TBD OK
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Xilinx XCF `xcf01s, xcf02s, xcf04s <https://www.xilinx.com/products/silicon-devices/configuration-memory/platform-flash.html>`__ NA OK
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Xilinx Zynq7000 `xc7z010, xc7z020 <https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html>`__ OK NA
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Xilinx ZynqMPSoC `xczu2cg <https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html>`__ OK NA
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============= =================================================================================================================================== ====== =====
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.. include:: fpga.inc
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* IF: Internal Flash
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* AS: Active Serial flash mode
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15
doc/conf.py
15
doc/conf.py
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@ -11,8 +11,12 @@ ROOT = Path(__file__).resolve().parent
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sys_path.insert(0, abspath("."))
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from boards import ReadDataFromYAML, DataToTable
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from data import (
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ReadBoardDataFromYAML,
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BoardDataToTable,
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ReadFPGADataFromYAML,
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FPGADataToTable
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)
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# -- General configuration ------------------------------------------------
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@ -111,4 +115,9 @@ extlinks = {
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# -- Generate partial board compatibility page (`board.inc`) with data from `boards.yml`
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with (ROOT / "compatibility/boards.inc").open("w", encoding="utf-8") as wptr:
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wptr.write(DataToTable(ReadDataFromYAML()))
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wptr.write(BoardDataToTable(ReadBoardDataFromYAML()))
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# -- Generate partial FPGA compatibility page (`fpga.inc`) with data from `FPGAs.yml`
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with (ROOT / "compatibility/fpga.inc").open("w", encoding="utf-8") as wptr:
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wptr.write(FPGADataToTable(ReadFPGADataFromYAML()))
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@ -1,3 +1,4 @@
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from typing import List, Union
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from pathlib import Path
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from dataclasses import dataclass
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from yaml import load as yaml_load, Loader as yaml_loader, dump as yaml_dump
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@ -18,13 +19,13 @@ class Board:
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Constraints: str = None
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def ReadDataFromYAML():
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def ReadBoardDataFromYAML():
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with (ROOT / 'boards.yml').open('r', encoding='utf-8') as fptr:
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data = [Board(**item) for item in yaml_load(fptr, yaml_loader)]
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return data
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def DataToTable(data, tablefmt: str = "rst"):
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def BoardDataToTable(data, tablefmt: str = "rst"):
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def processConstraints(constraints):
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if constraints is None:
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return None
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@ -46,3 +47,36 @@ def DataToTable(data, tablefmt: str = "rst"):
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headers=["Board name", "Description", "FPGA", "Memory", "Flash", "Constraints"],
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tablefmt=tablefmt
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)
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@dataclass
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class FPGA:
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Model: Union[str, List[str]]
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Description: str
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URL: str = None
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Memory: str = None
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Flash: str = None
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def ReadFPGADataFromYAML():
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with (ROOT / 'FPGAs.yml').open('r', encoding='utf-8') as fptr:
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data = yaml_load(fptr, yaml_loader)
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for vendor, content in data.items():
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data[vendor] = [FPGA(**item) for item in content]
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return data
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def FPGADataToTable(data, tablefmt: str = "rst"):
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return tabulate(
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[
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[
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vendor,
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f"`{item.Description} <{item.URL}>`__",
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item.Model if isinstance(item.Model, str) else ', '.join(item.Model),
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item.Memory,
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item.Flash
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] for vendor, content in data.items() for item in content
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],
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headers=["Vendor", "Description", "Model", "Memory", "Flash"],
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tablefmt=tablefmt
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)
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