f6afb5ab9f
Add support for Digilent Anvyl, the Big Red Board.
...
Programming to SRAM works. Programming flash works with a renamed
spiOverJtag bitfile - cs(g)484 is different from fg(g)484, but the
configuration flash IOs all end up on the same pads in the end.
2025-04-26 23:49:24 -07:00
7a509b56ee
Merge pull request #541 from bl0x/numato-neso-support
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Add support for Numatolab Neso board.
2025-04-24 06:59:25 +02:00
ff1e77debf
adds GCM board type and FT4232H interface B cable
2025-04-23 07:04:40 -06:00
bdeb74b61e
Add support for Numatolab Neso board. Programming SRAM over USB works, when board jumpers are set for JTAG programming mode. SPI flashing does not work properly (does not boot).
2025-04-21 21:17:54 +02:00
fa1d328b93
esp_usb_jtag: new cable
...
- copy dirtyjtag to esp_usb_jtag, it compiles
- copy protocol definiton, defines and private data/struct from openocd esp_usb_jtag.c
- ulx3s_esp board with esp32s3 cable
- esp_usb_jtag specify usb vid:pid in jtag.cpp
- hardcode usb interface and endpoints
- getting caps
- set chip id (not applicable for fpga)
- tms write done, untested
- cleanup and toggle clk
- 32bit counting
- setting divisor (todo read base freq)
- div range within 1-255
- base speed from descriptor
- fix doc typo with swapped tms/tdi some cleanup but it doesn't work.
2025-04-18 07:32:15 +02:00
1bb69dcf22
kcu105: add fpga package in description
2025-03-20 20:09:46 +01:00
564485036e
doc/boards: added alinx_ax7201/alinx_ax703 entries.
2025-02-27 06:44:52 +01:00
c0cfc0cc57
Added alinx_ax7203 and alinx_ax7201 boards
2025-02-27 04:13:42 +01:00
2ff215dfff
board, efinix: added SPI variant for efinix t20 BGA256 board
2025-02-24 20:33:01 +01:00
c4d4e8db7e
doc/boards.yml, src/board.py: added tangconsole entry
2025-02-15 11:39:37 +01:00
5847ec2666
doc/boards.yml,src/board.hpp: fixed ac701 device code
2025-01-15 06:57:42 +01:00
f4fee37cea
Added STEP-MXO2_V2 board support.
2025-01-11 23:14:36 +08:00
79cf67e964
Added STEP-MAX10 V1 support.
2025-01-10 07:39:30 +08:00
f6f48a7b27
Add support for VCU108 board and Virtex UltraScale
2024-11-12 23:51:55 +01:00
ad01d986c1
adding support for cyc5000
2024-08-24 21:32:00 -07:00
9edf1edb3f
board, doc: added KNJN Dragon-L PCI Express & HDMI FPGA board (Spartan6 xc6slx25tcsg324
2024-08-03 09:22:49 +02:00
7e4b42b795
Adding support for AMD Virtex 7 FPGA VC709 Connectivity Kit Board
2024-07-12 23:32:14 -03:00
e3f315a121
Add support for Numato Systems Mimas A7 board.
2024-06-22 08:03:14 -04:00
26b4516aeb
added lilygo-t-fpga board (based on gwu2x #434 )
2024-05-20 21:18:20 +02:00
55b094ce00
add EP4CGX150
2024-04-27 16:18:23 +07:00
99147efa27
board,doc: added CERN SPEC45 support
2024-03-28 22:15:17 +01:00
bcbd8aa0e3
new board: olimex_gatemateevb Olimex GateMate A1 EVB
2024-03-03 08:25:55 +01:00
f57abf9024
Add Trenz TEC0330 board.
2024-03-01 13:38:12 +01:00
ae39b2c556
board.hpp: Add TE0712-8 Board (XC7A200TFBG484)
2024-02-28 22:46:01 +01:00
a926ab9b88
Add (Cern) VMM3 board
2024-02-28 11:50:10 +01:00
0e99360d1c
Add (Cern) VEC_V6 Board
2024-02-28 11:50:10 +01:00
85d9ca5d20
board: added digilent cmoda7_15t
2024-02-26 21:18:33 +01:00
e923ef4059
lattice nexus boards: change from CABLE_DEFAULT (i.e. 6MHz) to CABLE_MHZ(1) (i.e. 1MHz)
...
as at 6MHz the download of bitstreams is not stable.
With "not stable" we mean that:
- when dealing with Certus/Crosslink, most of the times it works
- when dealing with CertusPro devices, most of the times it doesn't work
We think this is due to the size of the bitstream and the way that the
transmission/storing is handled on the receiving side (i.e. the FPGA).
2024-02-13 09:24:47 +01:00
1aaa1b37ac
board: add Antmicro LPDDR4 Tester board
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Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:29:12 +01:00
59f5759888
board: add Antmicro DDR5 Tester board
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:25:07 +01:00
17939d587e
board: add Antmicro DDR4 Tester board
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:23:27 +01:00
ed547ed893
boards: adding AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit
2023-12-11 12:23:37 +01:00
b70a3991cc
Add pynq-z1 board
2023-12-08 14:51:38 -05:00
2a2435ecbe
board: Xilinx KCU105 (Kintex Ultrascale xcku040)
2023-12-08 16:00:59 +01:00
46ce2e61a7
ALINX AX7101 board.
2023-10-28 17:22:42 +02:00
a87d689d83
ALINX AX7102 board.
2023-10-24 14:03:18 +02:00
b76a67963e
board: SiPEED tang Mega 138K
2023-10-24 06:11:53 +02:00
9a2fe6e157
board: SiPEED tang Primer 25K
2023-10-24 06:07:42 +02:00
dce0c050a7
board: add gr740-mini
2023-10-20 07:55:53 +02:00
5733ca29c3
fix lattice programming and add nexus boards
...
Fix to lattice programming:
we considered a svf file generated by Lattice Radiant-Programmer
and compared it with the current way lattice devices were programmed.
There were few differences dealing with configuration reset and REFRESH.
These fixes allow us to program an fpga when it is in a state
of error (e.g. there's no bitstream in the SPI Flash).
Lattice parts added:
- CertusPro FPGA
Nexus boards added:
- Certus Versa Evaluation board
- CertusPro Evaluation board
- CertusPro Versa Evaluation board
2023-10-11 09:52:45 +02:00
ad5ada90db
board: trion_t20_bga256_jtag support
2023-10-03 06:51:38 +02:00
afbf0c4ff8
board: adding @lambdaconcept ecpix5_r03 (ft4232)
2023-09-21 06:24:30 +02:00
9e91c31e31
Fixes for PVS errors
2023-09-01 22:30:24 +03:00
9d22d62a54
part/board: adding Avnet Mini-ITX
...
Adding the Avnet Mini-ITX dev board that uses the XC7Z100 Zynq-7000
device.
2023-08-07 17:06:02 +01:00
e3c8d6be1d
board: added QMTECH cyclone10 LP starter kit (10CL016YU484C8G)
2023-08-05 11:49:53 +02:00
91f2900f0c
add support for colorlight-i9+ board + spiOverJtag/spiOverJtag_xc7a50tfgg484.bit.gz
2023-06-30 11:36:32 +02:00
3e25a33346
boards: added support for 14bits 125MHz redpitaya board (7010)
2023-06-29 16:59:42 +02:00
9331bf7a6b
add sipeed tang nano 20k
2023-05-25 19:24:48 +08:00
873de96a3b
spiOverJtag: added efinix Titanium Ti60 support
2023-04-27 16:41:58 +02:00
07a0708eb8
efinix:
...
- jtag mode: added spiOverJtag support;
- spiOverJtag: added efinix support: verilog file and t8f81 bitstream
- xyloni: part code for spiOverJtag flash access/load bridge
2023-04-27 16:41:17 +02:00
Dusk
Gwenhael Goavec-Merou
Mike Goelzer
Bastian Löher
Emard
bma
TarikHamedovic
steward-fu
Nicolas Schodet
Greg Steiert
Julio Nunes Avelar
Stéphane Potvin
Hans Baier
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
Uwe Bonnes
Giovanni Bruni
Michal Sieron
Tim Paine
Haakan T Johansson
Alexey Starikovskiy
Shareef Jalloq
Stéphane Chevigny
wonderfullook