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doc/boards: added alinx_ax7201/alinx_ax703 entries.

This commit is contained in:
Gwenhael Goavec-Merou 2025-02-27 06:44:52 +01:00
parent cfdb59b9e1
commit 564485036e
2 changed files with 15 additions and 1 deletions
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14
doc/boards.yml
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@ -13,6 +13,20 @@
Memory: OK
Flash: OK
- ID: alinx_ax7201
Description: AX7201 FPGA Dev Board & Kit with AMD Artix 7
URL: https://www.en.alinx.com/Product/FPGA-Development-Boards/Artix-7/AX7201.html
FPGA: Artix xc7a200tsbg484
Memory: OK
Flash: OK
- ID: alinx_ax7203
Description: AX7203 FPGA Dev Board & Kit with AMD Artix 7
URL: https://www.en.alinx.com/Product/FPGA-Development-Boards/Artix-7/AX7203.html
FPGA: Artix xc7a200tfbg484
Memory: OK
Flash: OK
- ID: litex-acorn-baseboard-mini
Description: The LiteX-Acorn-Baseboards are baseboards developed around the SQRL's Acorn board (or Nite/LiteFury)
URL: https://github.com/enjoy-digital/litex-acorn-baseboard/

2
src/board.hpp
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@ -111,8 +111,8 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("alinx_ax516", "xc6slx16csg324", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7101", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7102", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7201", "xc7a200tfbg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7203", "xc7a200tfbg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("alinx_ax7201", "xc7a200tfbg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_ddr4_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_ddr5_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_lpddr4_tester", "xc7k70tfbg484", "ft4232", 0, 0, CABLE_DEFAULT),