1789feb2cf
Rewrite GOWIN algorithms
2023-10-29 05:52:38 +01:00
cceac16fc5
precompute TMS sequencies
2023-10-21 08:17:19 +02:00
0bbf817c92
part: fix typo
2023-10-19 17:46:50 +02:00
32ef0bd29c
Adding xcku115 to parts list ( #394 )
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* Adding xcku115 to parts list
* Adding xcku115 to list of supported FPGAs
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Co-authored-by: Stephen Goadhouse <stephen.david.goadhouse@cern.ch>
2023-10-19 17:45:42 +02:00
f964c3364f
doc/FPGAs,boards: adding certus boards/parts entries
2023-10-13 17:12:13 +02:00
5a3ab610a5
Merge pull request #390 from bg-gsl/lattice_fix_program
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Lattice programming fix and boards added
2023-10-13 16:57:59 +02:00
cde4a2daf1
Merge pull request #392 from enjoy-digital/xc7a35tfgg484
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Add xc7a35tfgg484 support and bitstream.
2023-10-13 11:19:45 +02:00
ba0a2f3e26
spiOverJtag: Add xc7a35tfgg484 bitstream.
2023-10-13 11:13:47 +02:00
9de0f30137
spiOverJtag: Add xc7a35tfgg484 support.
2023-10-13 11:13:29 +02:00
ce3935a72b
Merge pull request #391 from enjoy-digital/xcku3p-ffva676-spiOverJtag
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Add xcku3p ffva676 SpiOverJtag support & bitstream.
2023-10-12 18:14:04 +02:00
ddac3df394
spiOverJtag: Add xcku3p-ffva676 bitstream.
2023-10-12 18:09:41 +02:00
87a21fe74e
spiOverJtag: Add xcku3p_ffva676 support.
2023-10-12 18:02:23 +02:00
7a637a1085
spiOverJtag/xilinx_spiOverJtag: Update code since Virtex Ultrascale has apparently been replaced with Xilinx Ultrascale.
2023-10-12 18:00:59 +02:00
dafe350fbe
lattice nexus family: REFRESH (plus config logic reset) in case of fpga in error state and add capabilities to handle the whole 64-bits status register
2023-10-12 09:06:54 +02:00
5733ca29c3
fix lattice programming and add nexus boards
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Fix to lattice programming:
we considered a svf file generated by Lattice Radiant-Programmer
and compared it with the current way lattice devices were programmed.
There were few differences dealing with configuration reset and REFRESH.
These fixes allow us to program an fpga when it is in a state
of error (e.g. there's no bitstream in the SPI Flash).
Lattice parts added:
- CertusPro FPGA
Nexus boards added:
- Certus Versa Evaluation board
- CertusPro Evaluation board
- CertusPro Versa Evaluation board
2023-10-11 09:52:45 +02:00
ec35f15a51
altera,efinix,gowin,xilinx: Fix 'Flash SRAM' -> 'Load SRAM'
2023-10-09 14:53:57 +02:00
3e37a915bc
Merge pull request #388 from pu-cc/gatemate-dirtyjtag
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gatemate: fix dirtJtag support
2023-10-04 17:56:20 +02:00
18056180a8
gatemate: do not call ftdi-related routines when using alternative cables
2023-10-04 15:41:10 +02:00
3ed1d0d61d
doc/board: fix efinix naming / mode
2023-10-03 06:54:22 +02:00
ad5ada90db
board: trion_t20_bga256_jtag support
2023-10-03 06:51:38 +02:00
e9b31425d6
cable: efinix jtag ft2232 variant
2023-10-03 06:48:47 +02:00
48caa612a3
Merge pull request #381 from openhardwarefan/xczu17eg_support
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Add support for Xilinx xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.
2023-09-23 06:42:00 +02:00
c0ad3225cc
Add support for Xilinx xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.
2023-09-22 19:33:01 -07:00
c82a8e6207
Make CH347 driver faster
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Speed up toggleClk
Defer write-only USB transactions to better utilize bus
2023-09-22 07:08:48 +02:00
67159e8297
Move JTAG chain bit init to device_select()
2023-09-22 07:05:20 +02:00
4c39abf51c
Add missing pieces to JTAG
2023-09-22 07:01:48 +02:00
85f9791600
drop div_by_5 to allow 2.5MHz clock
2023-09-22 06:55:21 +02:00
01ac90a172
[xilinx] add jtag->flush before sleep
2023-09-21 07:38:25 +02:00
b10be9ae8a
properly fill dummy arrays
2023-09-21 07:36:41 +02:00
d3410e0e30
Update JTAG chain detect
2023-09-21 07:33:54 +02:00
fc6f3fb8e1
doc/data: adding an (unused for now) SPIFlash entry
2023-09-21 07:03:41 +02:00
5bbc02f56b
doc/boards: fix wrong constraints link
2023-09-21 07:03:07 +02:00
afbf0c4ff8
board: adding @lambdaconcept ecpix5_r03 (ft4232)
2023-09-21 06:24:30 +02:00
6c16417ee9
Merge UPDATE_DR and UPDATE_IR handling in JTAG state machines
2023-09-20 07:59:34 +02:00
6a0de15bff
Parse LoadingRate field
2023-09-20 07:58:06 +02:00
0c89ac9a44
Add GD32VF103 to misc devices
2023-09-20 07:48:21 +02:00
94b62460c5
jtag: shiftDR: (fix daisy chain) when more than one FPGA, a sequence of '0' before and/or after must be sent instead of '1' ( fix #189 and #133
2023-09-17 08:59:26 +02:00
9810735e32
jtag: rework detectChain: try unmasked idcode first
2023-09-14 21:53:27 +02:00
57fc9bcb6f
part: machXO3: re-add partially revision
2023-09-14 21:52:53 +02:00
2c23e8a3b6
Merge pull request #376 from rarengifoArthrex/master
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pass along reset parameters to provide control to the caller
2023-09-11 06:14:08 +02:00
5e9cc7c440
pass along reset paramaters to provide control to the caller
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Upsteam-Status: Submitted [https://github.com/traucucayre/openFPGALoader ]
- Submitted to upstream, waiting approval
2023-09-10 20:46:08 -07:00
c417ce6746
lattice: spi_put: avoid loop when tx == NULL
2023-09-06 15:50:28 +02:00
61b59ce827
jtag: fix state machine (issue introduce by commit 9e91c3)
2023-09-06 15:47:32 +02:00
8989ac9768
Merge pull request #372 from aystarik/fixes
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Fixes
2023-09-02 07:18:44 +02:00
9e91c31e31
Fixes for PVS errors
2023-09-01 22:30:24 +03:00
fbb8341323
Merge pull request #370 from aystarik/master
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Generic refactoring of the code
2023-08-31 09:46:44 +02:00
0f3afbcaea
Make IDCODE unsigned
2023-08-29 20:01:21 +03:00
8976404b78
Use JTAG state
2023-08-29 20:00:28 +03:00
1908ccd83b
make output buffer const
2023-08-29 19:51:41 +03:00
d5c72dcc58
doc/FPGAs: adding Gowin GW5A serie
2023-08-12 07:41:18 +02:00
Alexey Starikovskiy
Gwenhael Goavec-Merou
sgoadhouse
Florent Kermarrec
Giovanni Bruni
Patrick Urban
Zhongyi Chen
Rodrigo Rengifo