Merge pull request #391 from enjoy-digital/xcku3p-ffva676-spiOverJtag

Add xcku3p ffva676 SpiOverJtag support & bitstream.

spiOverJtag/Makefile

@@ -11,6 +11,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xc7k160tffg676 \
 	xc7k325tffg676 xc7k325tffg900 \
 	xc7k420tffg901 \
+	xcku3p-ffva676 \
 	xcku5p-ffvb676 \
 	xcvu9p-flga2104 xcvu37p-fsvh2892
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))

spiOverJtag/build.py

@@ -96,6 +96,7 @@ if tool in ["ise", "vivado"]:
         "xc7s50csga324"    : "xc7s_csga324",
         "xcvu9p-flga2104" : "xcvu9p_flga2104",
         "xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
+        "xcku3p-ffva676" : "xcku3p_ffva676",
         "xcku5p-ffvb676" : "xcku5p_ffvb676",
         }[part]
     if tool == "ise":
@@ -141,6 +142,8 @@ if tool in ["ise", "vivado"]:
                     'paramtype': 'vlogdefine',
                     'description': 'secondary flash',
                     'default': 1}
+            elif part == "xcku3p-ffva676":
+                tool_options = {'part': part + '-2-e'}
             elif part == "xcvu37p-fsvh2892":
                 tool_options = {'part': part + '-2L-e'}
         else:

spiOverJtag/constr_xcku3p_ffva676.xdc

@@ -0,0 +1,7 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+# Table 1-2 from UG570
+set_property CFGBVS GND [current_design]
+
+# Primary QSPI flash
+# Connection done through the STARTUPE3 block

spiOverJtag/xilinx_spiOverJtag.v

@@ -1,6 +1,6 @@
 module spiOverJtag
 (
-`ifndef virtexultrascale
+`ifndef xilinxultrascale
 	output csn,
 
 `ifdef spartan6
@@ -13,7 +13,7 @@ module spiOverJtag
 	input  sdo_dq1,
 	output wpn_dq2,
 	output hldn_dq3
-`endif // virtexultrascale
+`endif // xilinxultrascale
 
 `ifdef secondaryflash
 	output sdi_sec_dq0,
@@ -60,7 +60,7 @@ module spiOverJtag
 	assign sck = drck;
 	assign runtest = tmp_up_s;
 `else // !spartan6 && !spartan3e
-`ifdef virtexultrascale
+`ifdef xilinxultrascale
 	wire [3:0] di;
 	assign sdo_dq1 = di[1];
 	wire [3:0] do = {hldn_dq3, wpn_dq2, 1'b0, sdi_dq0};
@@ -92,7 +92,7 @@ module spiOverJtag
 		.USRDONEO (1'b1), // 1-bit input: User DONE pin output control.
 		.USRDONETS(1'b1)  // 1-bit input: User DONE 3-state enable output.
 	);
-`else // !spartan6 && !spartan3e && !virtexultrascale
+`else // !spartan6 && !spartan3e && !xilinxultrascale
 	STARTUPE2 #(
 		.PROG_USR("FALSE"),  // Activate program event security feature. Requires encrypted bitstreams.
 		.SIM_CCLK_FREQ(0.0)  // Set the Configuration Clock Frequency(ns) for simulation.