* CPE mapping improvements
* Use CP_OUT for adders
* Fixes
* Small fixes
* Cleanups
* Cleanup
* Cleanups
* Fixes
* Fixes
* Optimize
* Cleanup
* clangformat
* Cleanup
* Cleanup
* Bump required version of database
* Cleanup
* Resolve name conflicts
* Fix signal routing
* Make CPE_LATCH separate
* Add more timings models, need updated values
* Fixed warning
* multiplier support from lofty/gatemate-mult
* explicitly zero some params in B passthrough
* comment the relevant CPE inputs in check_multipliers
* Rename some of bels
* remove _lower from name
* refactor multiplier checking
* Revert "remove _lower from name"
This reverts commit daa1041bdf.
* Fixe net name to be unique
* Make sure we at least generate bitstream with all info
* Simplify zero
* Bounded cell type in gui
* typo fix
* Remove A passthrough inversion option
* Clean up CarryGenCell config
* Update a passthru to use new primitives
* Cleanup for adders
* Clean up MsbRoutingCell
* Cleanup
* Refactor A connection code
* Make it more as in PR #1513
* Added cplines to bpassthru and fixed constant driver for A
* Add parts
* Added comp out connections
* clangformat
* clangformat
* Clean up B passthrough connections
* wire up a bunch of intermediate signals
* Bit of cleanup
* handing of C_EN_IN
* C_EN_CIN fixes
* connect f_route to its lines
* fix cite for FRoutingCell
* fixup, oops
* connect multfab to its lines
* Commented line
* Connect CPOUTs
* Handle C_I params
* connect CINY1 for CarryGenCell
* fix carry gen CINX
* Update L2T4 model
* Updates for ADDCIN
* clangformat
* fix some issues with multfab and f_route
* look at C_I when doing inversion
* Only set some C_I signals when used
* Fix one more place
* do not use cplines so we can merge in one cell
* Cover cases that could be optimized out
* clangformat
* Cleanups
* Disable multiplier usage for now
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Use loop enumeration of PIPs instead of direct name construction for the
upper and lower ends of the segment wire.
Also do not allow clock wires for segments.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* SER_CLK support
* Update constids
* wip
* CLK_FEEDBACK
* Handle SER_CLK and SER_CLK_N
* clangformat
* Cleanup
* Use _ as separator for PLL CFGs
* Remove unused clocking cells
* Do not use same name for IO models
* Fix IDDR merge
* Cleanup
* Properly handle user global signals
* Move signal inversion in bitstream creation
* Start adding multi die support
* Display die location for pins used
* Do not use constant s as locations
* Cleanup SB_DRIVE handling
* Use DDR locations from chip database
* Place only in prefered die for now
* Set D2D
* Fixed typos
A segment router replaces the source-to-sink connection by
general-purpose PIPs with bus-branch segment network connections.
The problem arises when the source is connected to the sinks directly
without switching as in the case of LUT->DFF, such wires should be left
as is, which is what this PR does.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Miodrag Milanovic
José Miguel Sánchez García
myrtle
YRabbit
Lofty
Frans Skarman
William D. Jones
Catherine