In some cases, wires with the same name were being re-created.
This affected both the creation of shared primitive ports and changing
the wire type if the cell had an additional function.
Here, we separate wire creation and type change into a separate function and use it in most cases.
Addresses: https://github.com/YosysHQ/nextpnr/issues/1759
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The MMCM fasm writer put the 10-bit BANDWIDTH loop-filter word into
FILTREG1_RESERVED[11:0] and wrote a hardcoded 0x3d4 into TABLE[9:0].
prjxray's TABLE[9:0] is the loop-filter table word; with the filter
word misplaced the MMCM analog loop is misconfigured and never
asserts LOCKED on hardware (clock outputs stay dead).
Swap them: TABLE[9:0] gets filter_lookup[CLKFBOUT_MULT-1],
FILTREG1_RESERVED[11:0] gets the constant 0x8, matching Vivado
bitstreams for the same configurations.
Also program POWER_REG from the actual configuration instead of
0xffff: 0x0100 for integer-only counters, 0x9900 when CLKOUT0 or
CLKFBOUT uses fractional divide, again matching Vivado (verified on
integer and CLKOUT0_DIVIDE_F=6.5 fractional testcases by diffing
against Vivado bitstreams).
Hardware-validated on xc7a100t (QMTech Wukong): MMCM-derived clocks
(integer and fractional configurations) lock and run; the same
designs never asserted LOCKED before this change.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Add bel.v3.txt, which carries per-arc BEL timing (Delay/SetupHold/
ClkToOut/Clock) with config-bit conditions, on top of bel.v2's structural
blocks. Timing is applied per instance: a representative per-type estimate in
prePlace, then each placed BEL's own arcs in postPlace (bel_timing_by_bel,
keyed by BelId).
Add placement_estimate.txt carrying BEL timing estimates and nextpnr
placer/router tunables (delayScale/delayOffset/delayEpsilon/ripupPenalty/
carryPredictDelay, each defaulting to nextpnr's historical hardcoded value).
A more detailed description of the FABulous model files can be found here:
https://fabulous.readthedocs.io/en/latest/user_guide/using_doc/pnr/nextpnr.html#bel-v3-txt-bel-timing
bel.v3.txt and placement_estimate.txt were added as separate files
to keep compatibility with older nextpnr versions and existing fabulous projects.
A few cosmetics and comments added.
This commit merges every main() for every uarch into asingle one.
This fixes a build error when building tests for every uarch at once.
Signed-off-by: gitRaiku <raraiku@proton.me>
When a PLL output is connected to a BUFG, it can only be connected to it.
The message is improved in mentioning it and listing all ports connected and the pll name.
This simplify debug.
Adding freeing of the addition/subtraction mode switch PIP.
We're limiting optimization to just one constant input—cases with two
constant inputs are rare, and this raises questions about how such ALUs
are generated in synthesis.
LUT knowledge calculations have been replaced with table
constants—faster and easier to verify.
Addresses https://github.com/YosysHQ/apicula/issues/514
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
0xa000
Jasper Homann
gatecat
YRabbit
Lunaphied
Jonas K.
Miodrag Milanovic
gitRaiku
Jasper Homann
Lofty
Michael Offel
mrcmry
Rowan Goemans
William D. Jones