In some cases, wires with the same name were being re-created.
This affected both the creation of shared primitive ports and changing
the wire type if the cell had an additional function.
Here, we separate wire creation and type change into a separate function and use it in most cases.
Addresses: https://github.com/YosysHQ/nextpnr/issues/1759
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
TMDS_33 differential outputs use the Y0 current-mode driver alone
(TMDS_33.OUT plus DRIVE.I_FIXED, with the Y1 pad set IN_ONLY). Vivado
bitstreams for the same design do not set the tile OUT_DIFF feature
for TMDS pairs, and setting it disables the driver stage entirely: on
hardware the attached HDMI monitor reports no transmitter present.
Emit OUT_DIFF only for non-TMDS differential outputs (e.g. LVDS_25),
matching Vivado.
Hardware-verified on xc7a100t (QMTech Wukong): 640x480 DVI output via
an onboard HDMI connector, dead without this change, working with it.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Add bel.v3.txt, which carries per-arc BEL timing (Delay/SetupHold/
ClkToOut/Clock) with config-bit conditions, on top of bel.v2's structural
blocks. Timing is applied per instance: a representative per-type estimate in
prePlace, then each placed BEL's own arcs in postPlace (bel_timing_by_bel,
keyed by BelId).
Add placement_estimate.txt carrying BEL timing estimates and nextpnr
placer/router tunables (delayScale/delayOffset/delayEpsilon/ripupPenalty/
carryPredictDelay, each defaulting to nextpnr's historical hardcoded value).
A more detailed description of the FABulous model files can be found here:
https://fabulous.readthedocs.io/en/latest/user_guide/using_doc/pnr/nextpnr.html#bel-v3-txt-bel-timing
bel.v3.txt and placement_estimate.txt were added as separate files
to keep compatibility with older nextpnr versions and existing fabulous projects.
A few cosmetics and comments added.
This commit merges every main() for every uarch into asingle one.
This fixes a build error when building tests for every uarch at once.
Signed-off-by: gitRaiku <raraiku@proton.me>
When a PLL output is connected to a BUFG, it can only be connected to it.
The message is improved in mentioning it and listing all ports connected and the pll name.
This simplify debug.
Adding freeing of the addition/subtraction mode switch PIP.
We're limiting optimization to just one constant input—cases with two
constant inputs are rare, and this raises questions about how such ALUs
are generated in synthesis.
LUT knowledge calculations have been replaced with table
constants—faster and easier to verify.
Addresses https://github.com/YosysHQ/apicula/issues/514
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
0xa000
gatecat
YRabbit
Lunaphied
Jonas K.
Miodrag Milanovic
gitRaiku
Jasper Homann
Lofty
Michael Offel
mrcmry
Rowan Goemans
William D. Jones
Patrick Urban