verilog netlists makes a difference to the matching (or failure
thereof), I applied the same in-circuit pin matching as previously
applied to mixtures of SPICE and verilog netlists. This is clearly
a more robust way to handle pin order differences between parent
and child than was implemented previously.
while back, shorted pins were moved into contiguous positions.
When that method was discovered to cause matching issues, it was
abandoned with a note that doing so might have unintended
consequences because other code might depend on the shorted pins
being contiguous. Such a case was just found, and corrected.
However, it was also found that shorted pins were still not
completely handled correctly in MatchPins(); a solution was
found that adds such pins to the "permutes" list (which needs to
be done if the shorted pins are to be correctly handled in any
higher level of the hierarchy, if there is one), and the
"permutes" list is then checked by MatchPins() to determine if
pins match because they belong to the same group of shorted
pins.
incorrectly evaluated; "(w+l)" for example treats "w+l" as
a single string instead of three tokens. Corrected the code
to watch for a failure of strtod() when parsing the expression
at the "+" sign (also for "-").
were not compared for sorting in the same way they are compared
for property matching. The "slop" value was treated as absolute,
not a percentage, so for example a slop of 0.01 on a dimension
of microns would cause all dimensions to be treated as round-off
error, and no sorting would occur.
before its component cells, and the component cells are read in as
SPICE netlists. Then the original verilog cell and its instances
need to have pins reordered to match the subcircuit definition in
the SPICE netlist. Otherwise, when verilog and SPICE netlists are
mixed, the order in which the files are read is critical, and
failures due to reading out-of-order are very obscure and nearly
impossible to debug.
the following: (1) Checking that the parent cell is verilog,
(2) only running after the two cells themselves have been compared
and matched, then (3) added the missing pin or pins while reordering
pins on instances (note: this may not work if the verilog netlist is
the first passed to netgen; that case needs to be checked).
(1) When a comment line follows a ".subckt" line, and the comment
line is empty or all whitespace, then the following line would
be ignored. This condition appears to be very specific and
was solved simply by detecting it and handling it.
(2) Occasionally the "M" parameter of a subcircuit will be recorded
as type double, and this was not being anticipated by the code
that checks if "M=1" matches a corresponding entry with no "M"
parameter. Simple fix to check the condition where the "M"
parameter is type double.
"-flat_namespace -undefined suppress -noprebind" to "-undefined
dynamic_lookup" which is what was done in magic, which has a
similar structure to netgen.
move to the start index before relinking the sorted entries. That
will cause properties to be lost whenever the start index is greater
than zero. Not sure why this hasn't been caught previously, or
whether other errors are involved here.
devices from a .prm file into class "subckt" when they should be
class "module" (because they are primitives). Otherwise, netgen
will crash when attempting to flatten them.
with IRSIM including recent changes made to support multiple device
types using the subcircuit "x" component type. This requires
reading in a .prm file, which incidentally can be used with any
SPICE file to inform netgen of the specific component type of any
model defined as a subcircuit.
the removal of zero-valued devices between ports on the top level
(from version 254 they are ignored for levels under the top to
prevent port order from getting scrambled). An invalid check was
being made to determine if the cells being compared were the top
of the compare queue. This has been fixed.
string vs. integer) will cause a segfault. Not sure if
type promotion is needed at that point because the failing case
was a syntax error that caused a double value to be interpreted
as a string because it could not be cast into a numeric form.
devices between two ports is ignored for top-level cells, because
the scrambled ports won't affect anything in that case, and the
error will be reported as a port error, as it should.
so that they are *not* removed to make a better match if they are
shorting across two ports. If removed, then the port lists will
get screwed up. It is better to let the subcircuits fail matching.
Then, after the mismatched subcircuits are flattened, if the zero-
valued resistor or voltage source no longer connects two ports, it
can be safely removed to make a better match.
response to Mitch Bailey's github issue #82:
(1) When skipping comments, skip the contents of "(* ... *)"
delimiters as well as "/* ... */" delimiters.
(2) When checking for qflow's "\abcd\" names (final space
replaced with a backslash for SPICE compatibility of
names), make sure that the last "\" is followed by end-
of-string. Otherwise names like "\a\bcd " will fail to
parse correctly.
when they are shorted, because doing so is scrambling the pin
order of cells with respect to the instance calls to the cell.
Not sure if there is any code that relies on shorted pins being
adjacent, though.
fault that would happen if the verilog had illegal syntax of a
misspelled net name (although normally netgen is expected not to
have to check the verilog for syntax, and there are probably many
such cases of netgen failing to handle incorrect verilog and then
crashing as a result).
tracks the output printed to stdout when matching pins. One section
of this subroutine used the wrong pointers when writing to the Tcl
list (for eventual JSON output) which was the fundamental error.
Beyond that, the "debug" case (if used) would fail to run some of
the matching code, and the "no matching pin" case needed to be
handled for the Tcl list output. Now the terminal output, terminal
debug output, and Tcl list output should all be in agreement on the
pin lists.
connected only to ports and not to any devices, then they do not
show up in NodeClasses() and so pass through most of the checks
in MatchPins(). A separate correspondence check is needed to make
sure that the same shorted ports appear in both netlists.
This is done by treating the loop variable as a temporary parameter
that is valid only inside the loop, and changing the parameter
value on each loop iteration. The file stream position is used
to iterate the loop with calls to fseek() and ftell(), so that the
input tokenizer continues to work within loops.
string for the setup file to be the "trivial default" previously
used in case of the setup file not being found. Put a newline
around the setup file messages so that they stand out from the
rest of the initial output information.
passed an invalid setup file, the netgen "lvs" script uses a
trivial default setup and issues no error or warning. Replaced
this behavior with an error message and a hard stop.
to have unique class hashes. This has the problem that it prevents
comparing N-to-1 cells because declaring X->X1 as equivalent breaks
the original name equivalence of X->X. The new implementation adds
the switch "-unique" to preserve the original behavior. Otherwise,
the class hashes are made the same as the 2nd cell passed to the
command, and it is the responsibility of the person running LVS to
ensure that this is done in the correct direction.
network parallel/series networks. Instead, added a global option
with command "property tolerance strict|relaxed" to reinstate the
original (strict) behavior on demand, while relaxing it by default.
This allows certain series/parallel networks to match numerically
even though the schematic netlist may have combined individual
devices.
with Tcl, since Tk is launched independently through the console
script and nothing inside of netgen itself involves graphics.
This prevents netgenexec from linking to Tk and X11 libraries.
the parallel sorting routine. This fixes occasional property
errors with series-connected devices such as resistors. (2) Added
a method to associate properties with specific pins when pins are
permutable. This allows netgen to properly check a value like
source/drain area when the definition of source and drain has
changed due to permutation of the device. (3) Added a "property"
command extension "associate" to associate a property with a pin,
for use with the method described in (2).
LVS result. The property matching was failing to match (M=1) to
(M!=1) if M was not registered as a property name (which it often
isn't). This would allow devices with different numbers of
instances in parallel to be put in the same matching group,
which then could later identify as a mismatch if the instances
were checked in a different order.
netgen is supposed to be checking properties for symmetry sorting,
but not reporting anything. This causes mysterious property
mismatch errors that don't actually exist to show up in the
output.
is that when the "class ignore" command is used, then ports of a
parent cell need to be checked for being disconnected if they
connect only to ports of an ignored/deleted child cell.
Tim Edwards
Donn
D. Mitch Bailey