777f7ef095Found a counting issue with netcmp output that will overrun the output string buffer if the size of the copied string is just the wrong amount, due to the use of strcpy() instead of strncpy() in at least one place. Just hacked a solution by allocating more space for the string, but this should be fixed properly. Also: Discovered that the "zero valued resistor" routine looks for shorted ports in the wrong place, and if it finds shorted ports it wrongly decides that the device it's looking at is a zero-valued resistor whether or not it really is zero-valued.
master
R. Timothy Edwards
2026-01-15 16:39:18 -0500
29ee16644dMerge branch 'master' into netgen-1.5
1.5.314
Tim Edwards
2025-12-29 02:00:02 -0500
9b4185fe62Reverted a change from a long time ago regarding removal of zero valued resistors connecting two ports. I do not recall exactly why I put that in but it appears to cause incorrect behavior.
R. Timothy Edwards
2025-12-28 14:54:07 -0500
f5147e5af6Merge branch 'master' into netgen-1.5
1.5.313
Tim Edwards
2025-12-12 02:00:03 -0500
ddd95c4fe6Added a few lines to the setup file parser so that if there is a missing brace in the file (a common error), then the fact that there is an unevaluated command when the file has finished being read will trigger an evaluation of the unfinished code and emit an error. Previously, the command and anything after the unterminated brace would just silently get ignored, which was not helpful for debugging setup syntax errors.
R. Timothy Edwards
2025-12-11 12:08:31 -0500
23b4e19204Merge branch 'master' into netgen-1.5
1.5.312
Tim Edwards
2025-12-09 02:00:02 -0500
c0c9993980Corrected a major error with the verilog parser. The verilog parser was not assigning the correct file number for the first input file, which resulted in the effect that if the first file read sets definitions for the netlist, then those definitions are wiped out on the following file read. There has been a workaround to read from /dev/null on the first file read so that the file number is set on all subsequent reads. This fix avoids the need for the workaround.
R. Timothy Edwards
2025-12-08 16:45:27 -0500
8a20b90074Corrected an issue that can cause a segfault in an incorrect run setup when a cell has no pins. Didn't really analyze the error condition, just caught and handled the condition to avoid the segfault.
R. Timothy Edwards
2025-12-08 13:09:50 -0500
5bb279a9e4Merge branch 'master' into netgen-1.5
1.5.311
Tim Edwards
2025-11-30 02:00:04 -0500
3392159243Added some extra code to the verilog parser. It now handles some additional syntax for wire bundles specified as a pin connection on an array of instances, and a few other things. These are not exhaustive but are solving an immediate problem. I will go back and clean up the code to make it work for more general cases later.
R. Timothy Edwards
2025-11-29 11:55:26 -0500
b2662b443fMerge branch 'master' into netgen-1.5
1.5.310
Tim Edwards
2025-11-25 02:00:02 -0500
24c6eb4cb9Updated the version to go along with the merge of pull request
R. Timothy Edwards
2025-11-24 12:26:57 -0500
9048191486Allow processing of cellnames with $. When loading a file, also print cellname on errors
Mitch Bailey
2025-11-25 00:51:06 +0900
Allow processing of cellnames with $. When loading a file, also print cellname on errors
Mitch Bailey
2025-11-25 00:51:06 +0900
1acef6c52cMerge branch 'master' into netgen-1.5
1.5.309
Tim Edwards
2025-11-22 02:00:02 -0500
72d7d55bbeCorrected an issue with the "-noflatten" switch to "lvs", which is also a problem with the underlying "flatten prohibit" command option; in one place, the cell's subcircuits were being prohibited from being flattened, causing issues including a potential infinite loop.
R. Timothy Edwards
2025-11-21 15:52:14 -0500
7459b6dfe8Merge branch 'master' into netgen-1.5
1.5.308
Tim Edwards
2025-11-13 02:00:02 -0500
04163aedccOne hopefully final modification to ensure that Tcl_InitStubs() uses the Tcl version that the program has been compiled to. This should work with both Tcl 8.X and Tcl 9.X.
R. Timothy Edwards
2025-11-12 11:32:18 -0500
f7d35f9ccaAccidentally changed a file in the last commit which gets overwritten by "configure". Moved the modification to the source file that doesn't get overwritten.
R. Timothy Edwards
2025-11-12 09:55:29 -0500
601277e539Updated the revision number for the last set of changes.
R. Timothy Edwards
2025-11-12 09:19:52 -0500
73344329f8Made some updates for Tcl 9 compatibility; also changed the Makefile to pass EXTRA_CFLAGS for testing with "-std=c99" and "-std=gnu99". Made some additional corrections to ensure a clean compile using -std=gnu99.
R. Timothy Edwards
2025-11-12 09:17:46 -0500
7f2ab31143Merge branch 'master' into netgen-1.5
1.5.307
Tim Edwards
2025-11-12 02:00:02 -0500
08485d28a7Changed CONST and CONST84 everywhere in tclnetgen.c to "const". The capitalized version of this got removed from the Tcl headers as some point and is no longer valid. Added an include of "strings.h" to base/actel.c, which was missing it (uses strcasecmp() in the code, and needs the function declaration).
R. Timothy Edwards
2025-11-11 09:59:14 -0500
45164bbf98Merge branch 'master' into netgen-1.5
1.5.306
Tim Edwards
2025-11-08 02:00:04 -0500
2ee286efb4Corrected the pin permutation check for pin matching; previously, this was not doing the correct cross-check, instead looking in the same netlist for the permutable pin and checking its node number, which is useless since the node number is the same by definition for permutable pins. This error would result in occasional false negative results during pin matching, showing matching where pins are actually not matched.
R. Timothy Edwards
2025-11-07 14:06:22 -0500
46cb8d6637Merge branch 'master' into netgen-1.5
1.5.305
Tim Edwards
2025-10-24 02:00:04 -0400
dae6919d4fUpdating the version to go along with the merge of pull request
R. Timothy Edwards
2025-10-23 09:54:36 -0400
017bdc6e48Changed nested to static variable. Otherwise gets reset with each line.
D. Mitch Bailey
2025-10-23 08:30:08 +0000
2825b786b7Merge branch 'master' into netgen-1.5
1.5.304
Tim Edwards
2025-10-23 02:00:04 -0400
b371af9235Corrected an error that was assumed to have been fixed three years ago (and may have been, but only under limited circumstances). Do to several errors, using "-noflatten" on the command line and using "flatten prohibit" in a script would not prevent cells from being flattened; the "-noflatten" list needed to be used to call "flatten prohibit", and "flatten prohibit" needed to be fixed to flag the specified cell instead of the top level cell where it exists.
R. Timothy Edwards
2025-10-22 10:43:00 -0400
0af8c7ad49Merge branch 'master' into netgen-1.5
1.5.303
Tim Edwards
2025-10-10 02:00:03 -0400
b5432d139bCorrected a corner-case where a module with no ports in verilog was creating an implicit net for the stand-in "(no pins)" port.
R. Timothy Edwards
2025-10-09 10:36:41 -0400
0aa20dcf62Merge branch 'master' into netgen-1.5
1.5.302
Tim Edwards
2025-10-09 02:00:04 -0400
0e958bd45cCorrected an issue in which black-box entries (such as low-level subcircuit devices) do not output information about mismatched pins. This can end up being treated as a non-error but the mismatch should be noted in the output regardless.
R. Timothy Edwards
2025-10-08 10:03:35 -0400
7cbf15aab1Merge branch 'master' into netgen-1.5
1.5.301
Tim Edwards
2025-10-03 02:00:02 -0400
b59196fa81Modified the SPICE file read routine to accept the CDL syntax "*.GLOBAL" as equivalent to ".GLOBAL". Corrected the property matching to handle property combination when no "critical" property is given. Critical properties exist when one property must remain constant and equal for other properties to combine, such as transistor length. But, for example, capacitors can combine area without any restriction based on another property. Also, corrected the property matching code to allow more than one property to be additive (example: capacitor area and perimeter). Corrected the equation for adding properties in parallel combination.
R. Timothy Edwards
2025-10-02 12:33:28 -0400
1de6f88f1eMerge branch 'master' into netgen-1.5
1.5.300
Tim Edwards
2025-09-10 02:00:02 -0400
6e6e9fb73fAdded code to catch and print an error in connectivity between a port and an internal node which can be missed when pin permutations are present. Previously, that could produce a situation where netgen would report a "port error" but otherwise list all ports as matching. Because the permutation handling makes this hard to detect while generating pin correspondence output, the non-matching pins are listed separately at the end, and only if no mismatch was detected during output.
R. Timothy Edwards
2025-09-09 13:45:29 -0400
33fed391fdMerge branch 'master' into netgen-1.5
1.5.299
Tim Edwards
2025-09-01 02:00:02 -0400
e84700a607Added a NULL check at one point in the SPICE read routine that prevents a segfault under some condition (not fully investigated) involving .include files. Appears to resolve the problem without any unintended consequences.
R. Timothy Edwards
2025-08-31 16:52:35 -0400
5f5248b3d0Merge branch 'master' into netgen-1.5
1.5.298
Tim Edwards
2025-08-27 02:00:03 -0400
0bee21ccc8Corrected an issue in which a property error in a subcell would not be reported at the end if there was a port error. This is important because port errors often resolve themselves, but the cell should not be reported clean if the port errors resolved but it had property errors. Also: Added a method to derive area and/or perimeter properties from length and width, so that capacitors can be combined in parallel without regard to which dimension is width and which is length. This feature has only been lightly tested.
R. Timothy Edwards
2025-08-26 17:47:46 -0400
80f9263004Merge branch 'master' into netgen-1.5
1.5.297
Tim Edwards
2025-08-26 02:00:02 -0400
c269f1de89Corrected an unexpected corner-case error in which if a newline in a spice netlist falls exactly on the last non-null position of the input buffer after the buffer has been expanded to accept more input data, then the next line gets read in automatically, and the newline gets treated as whitespace and not a newline.
R. Timothy Edwards
2025-08-25 10:31:19 -0400
edb50746cbMerge branch 'master' into netgen-1.5
1.5.296
Tim Edwards
2025-08-19 02:00:02 -0400
4443826f9eCorrected a place in netcmp.c where a new instance net connection is created without setting the cell name or instance name. That can cause a crash condition when attempting to locate the instance from the net record.
R. Timothy Edwards
2025-08-18 10:37:36 -0400
f2368ca223Merge branch 'master' into netgen-1.5
1.5.295
Tim Edwards
2025-05-18 02:00:02 -0400
a60dac6124Modified the primary SPICE token reading routine so that the call to strdtok() can differentiate between reading verilog and reading SPICE. Otherwise, SPICE containing the (dubious) syntax of using backslashes in names will get treated as a verilog name with verilog backslash notation, with generally undesirable results. When called from the SPICE reading routine, backslashes are treated as-is and not as verilog notation.
R. Timothy Edwards
2025-05-17 20:29:38 -0400
ee93d52a26Merge branch 'master' into netgen-1.5
1.5.294
Tim Edwards
2025-03-26 02:00:02 -0400
bbe645f0abCorrected an error in which netgen was trying to reduce an expression in a property that was not necessarily a parameter, and if it wasn't, then netgen would crash. Surfaced by an example using complicated parameters that netgen was apparently unable to handle (an issue for another day; the main goal here was to avoid a segmentation violation).
R. Timothy Edwards
2025-03-25 17:00:58 -0400
ba7004fd5bMerge branch 'master' into netgen-1.5
1.5.293
Tim Edwards
2025-03-10 02:00:02 -0400
4f315d33d6Fixed a corner case found by Sylvain Munaut (see github issue tracker #96) in which a subcircuit with only one port (in this case, a pad) but which has properties (in this case, "M") will fail to set the pointer position ahead of the property because the loop starts after the first pin, so it has already missed the position that needs to be saved. Fixed by initializing the value to the first pin position before starting the loop.
Tim Edwards
2025-03-09 11:07:58 -0400
704bfbc871Merge branch 'master' into netgen-1.5
1.5.292
Tim Edwards
2025-02-10 02:00:03 -0500
4457248ecdCorrected a long-standing issue with permutation, which turned out to be caused by failing to have a systematic way of determining which pin's hash value would be used for the hash value of all the pins. Because equivalent cells in the two netlists may have pins in different order, it was possible that they might end up with different hashes. This was solved simply by always taking the larger hash value of the two pins belonging to the permutable pair. Now permutation works correctly for arbitrary subcircuits. (Previously it worked for low-level components like MOSFETs because the pin order is always the same.)
Tim Edwards
2025-02-09 21:26:54 -0500
7bee1851faMerge branch 'master' into netgen-1.5
1.5.291
Tim Edwards
2025-01-05 02:00:04 -0500
021dfa6e8aMade changes to tkcon.tcl to ensure compatibility with Tcl version 9.
Tim Edwards
2025-01-04 14:18:21 -0500
e4a4621b96Merge branch 'master' into netgen-1.5
1.5.290
Tim Edwards
2025-01-02 02:00:01 -0500
1d286f9973Corrected an issue with generating proxy pins that had previously forced flattening to be done whenever any pin mismatch occurred, which undermined the whole proxy pin method. With the proxy pins fixed, reinstated the method of avoiding flattening when pin issues can be trivially corrected. Also: Added output to the pin matching for one mismatch case that was being missed.
Tim Edwards
2025-01-01 13:27:39 -0500
3ca77300acMerge branch 'master' into netgen-1.5
1.5.289
Tim Edwards
2024-12-28 02:00:02 -0500
6d2ef396efAfter giving the previous code change some more thought, I decided that it is beneficial to break symmetries by net name; it's just that net names should not be used before all symmetries related to pins have been broken. So I rewrote the compare routine to take an argument allowing or disallowing net name matches, and make one call to break symmetries by pin name followed by another call to break symmetries by net name. This still solves the original problem, but does not allow symmetries to be broken randomly on internal nets if names have been matched in both netlists. Otherwise the output may report nets that appear to be swapped, making the output confusing.
Tim Edwards
2024-12-27 16:20:00 -0500
2483b7440fCorrected an error in "ResolveAutomorphsByPin" where the code states to check that the nodes with matching names are pins, but never does. This results in an attempt to resolve automorphs by matching pin names AND net names. However, net names can match without the nets matching, as pointed out by Andrey Bondar (private communication). Fixed simply by adding the specified check that the node being name- matched is actually a pin.
Tim Edwards
2024-12-26 21:20:24 -0500
236fba18aaMerge branch 'master' into netgen-1.5
1.5.287
Tim Edwards
2024-11-15 02:00:04 -0500
49c0de0433Corrected an error found by Sylvain Munaut and discussed on open-source-silicon slack on Nov. 3 in which the simple verilog expression "assign name1 = name2[a:b]"; this revealed an error where the parsing of "name2" was being incorrectly run with GetBusTok() which must be called when the token starts with "[". This problem existed both for the left-hand-side parsing and the right-hand-side parsing, and has been fixed for both (where either side may be a subset of a bus and the other a complete bus).
Tim Edwards
2024-11-14 21:28:51 -0500
3b9dca0cf2Implemented the patch from Sylvain Munaut in github PR#90 (issue that the position in the code has shifted quite a bit and I don't really trust that git will do a clean merge.
Tim Edwards
2024-11-14 20:39:19 -0500
1272ed22feMerge branch 'master' into netgen-1.5
1.5.286
Tim Edwards
2024-10-20 02:00:02 -0400
7d910b616cModified the string matching "matchnocase()" routine to compare a verilog escaped string against an equivalent non-escaped string (requires that the escaped string differs from the non- escaped string by having a "\" at the front and " " at the end. The space character is always maintained as part of the string).
Tim Edwards
2024-10-19 17:07:09 -0400
6179ba8cb8Merge branch 'master' into netgen-1.5
1.5.285
Tim Edwards
2024-10-17 02:00:02 -0400
b1032f846bRefactored code in netcmp.c involved in printing side-by-side formatted output to make it much cleaner and easier to read. This is in preparation of correcting the circuit1<-->circuit2 asymmetry in the MatchPins() routine.
Tim Edwards
2024-10-16 20:38:44 -0400
4c546d1472Corrected an error that prevents property errors from being printed in detail if a port error is also found.
Tim Edwards
2024-10-16 09:44:48 -0400
aaf8fefc1aMerge branch 'master' into netgen-1.5
1.5.284
Tim Edwards
2024-10-16 02:00:02 -0400
e1aa231db1Corrected another error discovered by Andrei Bondar in which the critical property (e.g., L for transistors) is required to match exactly between devices in order to allow the additive property (e.g., W for transistors) to be summed. The critical property should match if all values are within the slop value, for floating-point values. Note: The implementation is still not rigorous, as the saved critical value may shift from device to device; so comparing, e.g., 1.00 to 1.01 to 1.02 to 1.03, etc., can find that all individual comparisons are within the slop value even though the slop is exceeded across all values.
Tim Edwards
2024-10-15 20:52:23 -0400
abaf896f7fMerge branch 'master' into netgen-1.5
1.5.283
Tim Edwards
2024-10-15 02:00:02 -0400
df8fa29b2fFixed an issue with property matching that was preventing the last- ditch effort of matching based on combining devices with the same critical property (e.g., adding gate widths together for transistors of the same gate length, if the property records remain stubbornly mismatched to the end). Thanks to Bondar Andrey Renatovich for surfacing this issue and providing a reproducible example.
Tim Edwards
2024-10-14 13:24:35 -0400
e94d25b3f1Merge branch 'master' into netgen-1.5
1.5.282
Tim Edwards
2024-10-08 02:00:03 -0400
d14bf70f1cWorking to get some MatchPins improvements from Mitch Bailey from a long time ago into the code. The improvements collided with intervening changes to the same routines and would not merge cleanly, which is why they were never merged. Step 1: Show the net name of a matching net that is missing a pin. Remove output of missing pins that is redundant (pin names being output twice).
Tim Edwards
2024-10-07 11:10:33 -0400
e659495ef5Merge branch 'master' into netgen-1.5
1.5.281
Tim Edwards
2024-10-04 02:00:03 -0400
5c21000a8bMade a modification to accommodate the situation where a SPICE instance is matched to a verilog module definition, and the SPICE instance is read before the verilog definition, forcing a placeholder cell to be created. Netgen will now make the assumption that the verilog ports are in the same order as the SPICE instance port order. At the same time, it will output a warning message that it is making this not-necessarily-warranted assumption. If the number of ports don't match or the placeholder did not come from a SPICE instance, then the placeholder pins are left alone.
Tim Edwards
2024-10-03 14:52:42 -0400
2ce3cf8dd9Merge branch 'master' into netgen-1.5
1.5.280
Tim Edwards
2024-10-03 02:00:02 -0400
05872ca918Corrected an apparently long-standing error that is responsible for some errors failing to list in the output while also being responsible for a number of non-errors showing up in the output. This fix may substantially clean up netgen output. Also: Added text to the output noting that pin matching may be incorrect with respect to symmetries if the nets have failed to match.
Tim Edwards
2024-10-02 21:20:27 -0400
05f433f334Merge branch 'master' into netgen-1.5
1.5.279
Tim Edwards
2024-10-01 02:00:02 -0400
e821381900Corrected a rather obscure error in which an otherwise unconnected port-to-port short (formed by "assign" in verilog or zero-valued resistors in SPICE) does not get checked when counting nodes before adding a proxy pin to a subcircuit in that cell, causing the proxy pin to be assigned the same node number and forming an unintended connection to the port-to-port connecting net.
Tim Edwards
2024-09-30 22:11:53 -0400
2129073a38Merge branch 'master' into netgen-1.5
1.5.278
Tim Edwards
2024-09-28 02:00:02 -0400
8022e1370fAdded a few lines to rebuild the node cache after removing devices such a zero-ohm resistors or zero-volt sources during the pre-match phase, since the list of nodes gets changed by merging nets across the removed devices. Otherwise, the node-name cache gets corrupted and random LVS errors occur.
Tim Edwards
2024-09-27 10:08:37 -0400
b0d980bb7dMerge branch 'master' into netgen-1.5
1.5.277
Tim Edwards
2024-08-17 02:00:03 -0400
2b88d79adcCorrected a rare case where a NULL value propagates in the flattening routine and is not caught until it causes a segfault.
Tim Edwards
2024-08-16 19:48:36 -0400
f2f082e627verilog: Create non-existent nodes if on LHS of `assign`
Sylvain Munaut
2024-05-20 12:59:42 +0200
ab0165b16cMerge branch 'master' into netgen-1.5
1.5.276
Tim Edwards
2024-05-17 02:00:02 -0400
bf4112db07Corrected two statements that can cause a segfault because a structure variable is not checked for the condition of being NULL before attempting to read a component of the structure. These conditions imply that something is badly wrong in the netlist but should not be causing a segfault.
Tim Edwards
2024-05-16 11:49:56 -0400
5197eb6186Merge branch 'master' into netgen-1.5
1.5.275
Tim Edwards
2024-05-15 02:00:01 -0400
fcee934580Corrected the parsing of the "model" command, which was failing to pass the right cell name to the routine which counts the number of pins. Using this in a setup file will prevent netgen from spending time matching low-level devices.
Tim Edwards
2024-05-14 15:12:41 -0400
48ed1f7583Merge branch 'master' into netgen-1.5
1.5.274
Tim Edwards
2024-05-10 02:00:02 -0400
2d427aef3cCorrected the bad placement of #ifdef TCL_NETGEN . . . #endif around critical parts of the netcmp.c code, causing issues with the non-Tcl build (not that anyone should be doing a non-Tcl build).
Tim Edwards
2024-05-09 14:11:26 -0400
e63593c7e2Merge branch 'master' into netgen-1.5
1.5.273
Tim Edwards
2024-04-04 02:00:01 -0400
fd0c8c87eaCorrected another error in which, for device sorting, "M" was set to 1 before the loop over devices in "run", resulting in "M" taking the value of the previous property record if the following record did not have an "M" value, instead of setting it to 1.
Tim Edwards
2024-04-03 21:05:08 -0400
3d180f778dCorrected an error that had previously been corrected in PropertyMatch() but not corrected symmetrically between circuit1 and circuit2; this left the possibility that "M=1" in one circuit vs. no "M" entry in the other would still pop up as a property error, depending on which circuit (layout or schematic) was listed first.
Tim Edwards
2024-04-03 11:01:58 -0400
Tim Edwards
Mitch Bailey
Dan Moore
luccareinehr
Sylvain Munaut