PropertyMatch() but not corrected symmetrically between circuit1
and circuit2; this left the possibility that "M=1" in one
circuit vs. no "M" entry in the other would still pop up as a
property error, depending on which circuit (layout or schematic)
was listed first.
verilog netlists makes a difference to the matching (or failure
thereof), I applied the same in-circuit pin matching as previously
applied to mixtures of SPICE and verilog netlists. This is clearly
a more robust way to handle pin order differences between parent
and child than was implemented previously.
while back, shorted pins were moved into contiguous positions.
When that method was discovered to cause matching issues, it was
abandoned with a note that doing so might have unintended
consequences because other code might depend on the shorted pins
being contiguous. Such a case was just found, and corrected.
However, it was also found that shorted pins were still not
completely handled correctly in MatchPins(); a solution was
found that adds such pins to the "permutes" list (which needs to
be done if the shorted pins are to be correctly handled in any
higher level of the hierarchy, if there is one), and the
"permutes" list is then checked by MatchPins() to determine if
pins match because they belong to the same group of shorted
pins.
were not compared for sorting in the same way they are compared
for property matching. The "slop" value was treated as absolute,
not a percentage, so for example a slop of 0.01 on a dimension
of microns would cause all dimensions to be treated as round-off
error, and no sorting would occur.
before its component cells, and the component cells are read in as
SPICE netlists. Then the original verilog cell and its instances
need to have pins reordered to match the subcircuit definition in
the SPICE netlist. Otherwise, when verilog and SPICE netlists are
mixed, the order in which the files are read is critical, and
failures due to reading out-of-order are very obscure and nearly
impossible to debug.
the following: (1) Checking that the parent cell is verilog,
(2) only running after the two cells themselves have been compared
and matched, then (3) added the missing pin or pins while reordering
pins on instances (note: this may not work if the verilog netlist is
the first passed to netgen; that case needs to be checked).
(1) When a comment line follows a ".subckt" line, and the comment
line is empty or all whitespace, then the following line would
be ignored. This condition appears to be very specific and
was solved simply by detecting it and handling it.
(2) Occasionally the "M" parameter of a subcircuit will be recorded
as type double, and this was not being anticipated by the code
that checks if "M=1" matches a corresponding entry with no "M"
parameter. Simple fix to check the condition where the "M"
parameter is type double.
"-flat_namespace -undefined suppress -noprebind" to "-undefined
dynamic_lookup" which is what was done in magic, which has a
similar structure to netgen.
move to the start index before relinking the sorted entries. That
will cause properties to be lost whenever the start index is greater
than zero. Not sure why this hasn't been caught previously, or
whether other errors are involved here.
devices from a .prm file into class "subckt" when they should be
class "module" (because they are primitives). Otherwise, netgen
will crash when attempting to flatten them.
with IRSIM including recent changes made to support multiple device
types using the subcircuit "x" component type. This requires
reading in a .prm file, which incidentally can be used with any
SPICE file to inform netgen of the specific component type of any
model defined as a subcircuit.
the removal of zero-valued devices between ports on the top level
(from version 254 they are ignored for levels under the top to
prevent port order from getting scrambled). An invalid check was
being made to determine if the cells being compared were the top
of the compare queue. This has been fixed.
string vs. integer) will cause a segfault. Not sure if
type promotion is needed at that point because the failing case
was a syntax error that caused a double value to be interpreted
as a string because it could not be cast into a numeric form.
response to Mitch Bailey's github issue #82:
(1) When skipping comments, skip the contents of "(* ... *)"
delimiters as well as "/* ... */" delimiters.
(2) When checking for qflow's "\abcd\" names (final space
replaced with a backslash for SPICE compatibility of
names), make sure that the last "\" is followed by end-
of-string. Otherwise names like "\a\bcd " will fail to
parse correctly.
fault that would happen if the verilog had illegal syntax of a
misspelled net name (although normally netgen is expected not to
have to check the verilog for syntax, and there are probably many
such cases of netgen failing to handle incorrect verilog and then
crashing as a result).
tracks the output printed to stdout when matching pins. One section
of this subroutine used the wrong pointers when writing to the Tcl
list (for eventual JSON output) which was the fundamental error.
Beyond that, the "debug" case (if used) would fail to run some of
the matching code, and the "no matching pin" case needed to be
handled for the Tcl list output. Now the terminal output, terminal
debug output, and Tcl list output should all be in agreement on the
pin lists.
connected only to ports and not to any devices, then they do not
show up in NodeClasses() and so pass through most of the checks
in MatchPins(). A separate correspondence check is needed to make
sure that the same shorted ports appear in both netlists.
passed an invalid setup file, the netgen "lvs" script uses a
trivial default setup and issues no error or warning. Replaced
this behavior with an error message and a hard stop.
to have unique class hashes. This has the problem that it prevents
comparing N-to-1 cells because declaring X->X1 as equivalent breaks
the original name equivalence of X->X. The new implementation adds
the switch "-unique" to preserve the original behavior. Otherwise,
the class hashes are made the same as the 2nd cell passed to the
command, and it is the responsibility of the person running LVS to
ensure that this is done in the correct direction.
network parallel/series networks. Instead, added a global option
with command "property tolerance strict|relaxed" to reinstate the
original (strict) behavior on demand, while relaxing it by default.
This allows certain series/parallel networks to match numerically
even though the schematic netlist may have combined individual
devices.
with Tcl, since Tk is launched independently through the console
script and nothing inside of netgen itself involves graphics.
This prevents netgenexec from linking to Tk and X11 libraries.
the parallel sorting routine. This fixes occasional property
errors with series-connected devices such as resistors. (2) Added
a method to associate properties with specific pins when pins are
permutable. This allows netgen to properly check a value like
source/drain area when the definition of source and drain has
changed due to permutation of the device. (3) Added a "property"
command extension "associate" to associate a property with a pin,
for use with the method described in (2).
LVS result. The property matching was failing to match (M=1) to
(M!=1) if M was not registered as a property name (which it often
isn't). This would allow devices with different numbers of
instances in parallel to be put in the same matching group,
which then could later identify as a mismatch if the instances
were checked in a different order.
netgen is supposed to be checking properties for symmetry sorting,
but not reporting anything. This causes mysterious property
mismatch errors that don't actually exist to show up in the
output.
is that when the "class ignore" command is used, then ports of a
parent cell need to be checked for being disconnected if they
connect only to ports of an ignored/deleted child cell.
then flattening instances of that cell can cause a port of the parent
cell connected to the disconnected port of the child cell to itself
become disconnected. If the parent port is not changed to show the
disconnected state, then pin mismatch can occur if the netlist being
matched didn't have the same flattened subcell. This condition is
now detected and handled correctly.
underlying issue (which needs to be investigated), but it does
prevent netgen from crashing when it encounters it (netgen will
generate an erro message instead).
to the JSON format file (since JSON does not allow single backslash
characters. Previously nets had been handled correctly, but not
pins. Resolves github issue tracker Issue #60 from Proppy.
significant overhaul of the MatchPins() code, and better handles
issues with pins disconnected from nets and removes cases in
which proxy pins are incorrectly generated.
request #59 ("Pin match"). Because the pull request has rather
sweeping modifications, I am doing this in two steps. The change
that most breaks with existing comparison methods is in the
PinMatch() routine in netcmp.c, where the method of generating
proxy pins has been removed. There are specific cases for which
the proxy pin method exists, although these were coping with
issues arising from extraction in magic which have been dealt
with to some extend. Possibly the proxy pin method is no longer
needed. So the PinMatch() changes will be done in a second
commit where it's easier to revert or modify the changes without
affecting the modifications from this commit.
command option "flatten prohibit" (or "flatten deny") to prevent
a subcell from being flattened at any time during the compare
process. Previously, the "-noflatten" option for the "lvs"
script had been used to prevent flattening during initial
pre-match, but if the circuit passed the prematch phase and
subcells were mismatched, they would be flattened regardless of
whether or not they were listed by the "-noflatten" option. This
also codifies a way to prevent subcells from being flattened in
the setup file rather than in the "lvs" command line. Also:
Found and fixed a bug that prevents the use of "-noflatten=" with
a cell name or list of cell names instead of a filename.
second one of them, which is a failure to change CurrentTail when
an extra (implicit) pin was added to the last component in the
current cell, resulting in the failure of Node() to add the new
no-connect node, which instead overwrites the pin just created.
were implicit in the first instances but made explicit in a later
one. If more than one such implicit pin was handled for the same
cell, then the pin count would become wrong and rather unpredictable
behavior results.
even when the opposing netlist has a black-box entry for the same
cell. The black-box entry can't be flattened, so this just
results in the cell mysteriously disappearing from one side.
to a single net (as can be done with assignments in verilog or with
zero-voltage sources or zero-value resistors in SPICE). Corrected
an error in the SPICE netlist reader that prevented the proper use
of zero-voltage sources as net splitters.
delimiter set when parsing pin names (the correct delimiter set
was used in one place but not in another). Extended the pin
matching to include the minor hack of ignoring the backslash
before backslash-escaped verilog names when there is otherwise
no exact match, since many tools convert verilog to SPICE by
removing the backslash and trailing space. This avoids pin
mismatches in a known set of use cases.
definitions are handled correctly. Also: Added code to evaluate
simple expressions for array bounds. Previously the parser could
handle a value followed by "+" or "-" and a constant. Now it can
handle all basic arithmetic.
summary, so that the summary lists the total number of devices as well
as the number of devices after parallel optimization, in the form
"device_name (M->N)", where "M" is the total number of devices, and
"N" is the number of devices after parallel combination. This makes
the output somewhat more meaningful to the end user. Implementation
as discussed in github issue #47.
parallel devices are prepended rather than appended, which avoids
having to search for the end of what may be a rapidly increasing
linked list of properties. This reduces the amount of time spent
in the parallel combination code. Thanks to Anton Blanchard for
pointing out this inefficiency.
speed up the time needed to flatten an instance, and add clarity to the
output by specifying the file number for each cell name being modified
during the pre-match stage.
ended up in the repository, as pointed out by Mitch Bailey in github
issue #44. Added lvs_manager.py to .gitignore to prevent that from
happening again in the future.
marked as unneeded, so I simply removed the code rather than
debug the issue, which was that buses got the delimeters erased
for checking but never put back again. Also: Modified the verilog
reading code so that if an empty set "()" is given for a pin, then
the initial proxy, which is a single net with the name prefix
"_noconnect_", can be promoted to a bus if further processing
reveals it to be a bus and not a single-bit signal.
used when ob may be NULL. Added a check in front for ob == NULL.
Also: Changed the disconnected node alert so that it does not
mention nodes marked "port_mismatch_error". These are disconnected
by definition, will show up in the pin list, and printing them as
"disconnected pins" is just confusing to the end user.
should not be called after CreateTwoLists(). CreateTwoLists()
was being called in one case only to print the contents of the
cells, so that part was pulled out into a separate routine.
contents (previously wasn't done), and also added sorting for items with
non-matching names which have only one item in the group for each circuit
(so they must be matching in some sense). This makes the output a bit
more readable without re-enabling the compute-intensive sorting method
for non-matching entries.
print statement, and clarified the messages about non-matching
circuits at the end, all of them suggestions made by Mitch
Bailey (see issue #34 on github).
saying that pins were mismatched when pin matching was never run
accidentally resulted in pin matching not being applied to black-box
entries. This has been corrected.
pins on non-black-boxed circuits as it does not black-boxed circuits,
but specifically looking for pins that are disconnected on both sides,
since those do not appear in the node list and are not otherwise
handled. Otherwise, disconnected pins will appear to have disappeared
from the first netlist.
a final parallel or series combination needs to be done but there
are still multiple property records. The multiplier was being
incorrectly applied twice, causing an automatic mismatch in
parameter values.
swapped, so that if pin names are swapped on the top level, netgen will
report this as a final error message. Otherwise, the mismatch is only
reported back in the pin list where it is not obvious.
The algorithm is to run without exhaustive subdivision until the
last step because this is much faster. The final iteration must
be run with exhaustive subdivision on, or else it is possible to
have cells with swapped pins matching. The routines that resolve
automorphisms were setting exhaustive subdivision for the final
iteration. But simple "run converge" and "run resolve" were not.
add properties across multiple property records in the last matching
step, if there are still multiple properties and the values can be
combined. Previously, netgen had been assuming that there would only
be one property record left at this point, which is not true. This
shows up particularly for BSIM fingered devices, since "nf" is
ignored.
run to the end of the list of circuit elements. Also corrected
another issue caused by the flag to denote multiple no-connect pins,
which can be on an instance pin and so cannot share the data from the
instance record.
device with one or more no-connect pins. The flag that indicates a
no-connect pin was checked incorrectly, potentially causing obscure
and misleading property mismatch messages to be generated.
records, which were being ignored. This really only applies to
parallel subcircuits being flattened. To flatten correctly requires
that any circuit with N property records must be flattened into the
parent at least N times. To do: Must look for M > 1 records in the
properties and flatten (M - 1) additional times.
without netgen noticing---this behavior got broken by an
exception for "black box" circuits, but failed to check if the
circuit really was marked as a "black box" or not. Fixing that
revealed another issue with verilog implicit pins. Both issues
have now been corrected.
netgen. More work will be done later. Also: Removed the
derived file lvs_manager.py from the repository, and modified
the Makefile to remove it as part of "make clean".
other devices that do not have a "critical property" that determines
which properties can add together was flawed and messed up the sorting
of devices like transistors and resistors that do have a critical
property. Reworked the sorting order so that it makes sense for both
situations.
Also corrected a superficial issue with an attempt to print out an
instance name that doesn't exist. There is an underlying bug here
related to cells that have no pins and/or no contents which has not
been debugged. The fix just keeps netgen from segfaulting.
no pins at all. This overrides the default behavior of treating
empty cells as "black-box" entries, and avoids attempts to compare
cells like logo artwork.
different additive properties (like transistor width) to combine;
this is totally wrong and may have been left over from code written
before the routine was split into simple combinations (add similar
devices) and agressive combinations (e.g., add widths together).
Tim Edwards
D. Mitch Bailey