A configurable and approachable tool for FPGA debugging and rapid prototyping.
Go to file
Fischer Moseley 978937e4bc modify example design naming convention 2024-05-12 10:25:00 -07:00
.github add sponsor button 2024-05-11 11:52:35 -06:00
doc doc: change WaveDrom render branch to main 2024-04-14 16:11:46 -06:00
examples/verilog modify example design naming convention 2024-05-12 10:25:00 -07:00
src/manta add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00
test put test outputs in build/ 2024-03-06 16:40:54 -08:00
.gitignore banish all .Xil/ folders 2024-03-07 09:19:11 -08:00
LICENSE.txt add badges to readme 2023-02-04 13:17:22 -05:00
Makefile update docs 2024-03-07 12:25:30 -08:00
README.md pull latest from main 2024-03-06 11:31:35 -08:00
environment.sh add environment.sh for tool paths and serial ports 2024-03-06 11:26:31 -08:00
mkdocs.yml tidy DHCP counter 2024-02-19 13:53:04 -08:00
pyproject.toml add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00

README.md

Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping

run_tests build_docs License: GPL v3 Code style: black

Manta is a tool for getting information into and out of FPGAs over an interface like UART or Ethernet. It's primarily intended for debugging, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It lets you configure a series of cores on a shared bus via a YAML or JSON file, and then provides a Python API to each core, along with vendor-agnostic Verilog HDL to instantiate them on your FPGA.

For more information check out the docs: https://fischermoseley.github.io/manta