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luke/ verilator

SystemVerilog 0 0 0

Verilator open-source SystemVerilog simulator and lint system

rtl verilog cpp compilers verilog-simulator verilator systemc system-verilog

Updated 2026-09-08 17:08:34 +02:00

luke/ manta

Python 0 0 0

A configurable and approachable tool for FPGA debugging and rapid prototyping.

fpga verilog icestorm icestick debug xilinx

Updated 2026-08-26 19:08:35 +02:00

luke/ sv2v

Haskell 0 0 0

SystemVerilog to Verilog conversion

verilog yosys systemverilog conversion

Updated 2026-08-18 14:52:11 +02:00

luke/ UberDDR3

Verilog 0 0 0

Opensource DDR3 Controller

fpga verilog controller phy memory-controller ddr3-phy ddr3-controller ddr3

Updated 2026-06-12 06:11:53 +02:00