Fischer Moseley
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d8eeb65b8f
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fix pipelining in video_sprite exmaple
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2023-04-13 18:00:22 -04:00 |
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Fischer Moseley
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ba6100ce30
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import tutorial from yesterday, add mostly working bram core
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2023-04-12 11:47:50 -04:00 |
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Fischer Moseley
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12f498dc9a
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add cursed BRAM core implementation
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2023-04-10 14:38:29 -04:00 |
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Fischer Moseley
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1710da6f87
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update makefile to represent new functional sim locations
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2023-04-09 22:33:58 -04:00 |
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Fischer Moseley
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1d5245b999
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fix tests for CI
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2023-04-08 14:12:24 -04:00 |
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Fischer Moseley
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ab8582a570
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move building examples into makefile, add working logic analyzer test
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2023-04-03 23:47:36 -04:00 |
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Fischer Moseley
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0a4a1519c4
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clean up inferred BRAM, trim whitespace
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2023-04-03 21:20:58 -04:00 |
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Fischer Moseley
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df4d243b9a
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refactor test structure
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2023-04-02 20:33:50 -04:00 |
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Fischer Moseley
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839bd4f8e4
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update arg order for iverilog - seems to throw errors across versions/OSs
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2023-04-01 16:38:45 -07:00 |
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Fischer Moseley
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d5dfd3bbf3
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add boilerplate for API generation tests
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2023-03-23 23:50:09 -04:00 |
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Fischer Moseley
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a57b5908f2
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add verbose output to serial
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2023-03-23 18:10:52 -04:00 |
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Fischer Moseley
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500267798f
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add example instantiation to top of autogenerated output
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2023-03-19 10:57:32 -06:00 |
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Fischer Moseley
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2c51aa9a9a
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paritally imnplement io core autogeneration
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2023-03-16 09:38:17 -04:00 |
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Fischer Moseley
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11495fca61
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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Fischer Moseley
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fade794333
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add initialls logic_analyzer core
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2023-03-15 15:57:42 -04:00 |
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Fischer Moseley
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aa2ba43e8f
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rename lut mem to lut ram, add to manta generator
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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3fda03ec90
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break up hdl definition into multiple member functinos
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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334aa8c005
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refactor __init__.py to be object-oriented
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5e2f02ebd6
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add linting to makefile, update bus testbenches
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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4d9792702a
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clean up testbenches, add Makefile for sims
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2023-03-14 16:24:56 -04:00 |