Fischer Moseley
|
0bdfd9a5f7
|
tests: fix mem_core_hw
|
2024-10-08 11:42:10 -06:00 |
|
Fischer Moseley
|
a01b6981e2
|
tests: refactor to use Amaranth-native API
|
2024-10-08 11:42:10 -06:00 |
|
Fischer Moseley
|
b87f8cbc48
|
meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx
|
2024-07-17 18:51:05 -07:00 |
|
Fischer Moseley
|
71ec1174d1
|
add parameterized HW tests for all memory core modes
|
2024-03-06 14:53:27 -08:00 |
|
Fischer Moseley
|
d1a772784a
|
add environment.sh for tool paths and serial ports
|
2024-03-06 11:26:31 -08:00 |
|
Fischer Moseley
|
5d5a50042f
|
make model tracking automatic in memory core tests
|
2024-03-06 01:12:36 -08:00 |
|
Fischer Moseley
|
b00e4d0e60
|
revert wiring.Component instead of Elaboratable
|
2024-03-04 01:18:31 -08:00 |
|
Fischer Moseley
|
f83dc59b4e
|
add more MemoryCore tests
|
2024-03-04 00:17:36 -08:00 |
|
Fischer Moseley
|
08adbd8ede
|
switch to wiring.Component instead of Elaboratable
|
2024-03-03 19:10:06 -08:00 |
|
Fischer Moseley
|
b729deb144
|
hardcode device paths in hardware tests
|
2024-03-03 18:31:11 -08:00 |
|
Fischer Moseley
|
2e2397013e
|
make mem_core_hw tests pass
|
2024-03-02 14:08:52 -08:00 |
|
Fischer Moseley
|
6438a55192
|
partially revert MemoryCore updates
|
2024-03-02 13:31:01 -08:00 |
|
Fischer Moseley
|
6aea5cc6e1
|
update MemoryCore references
|
2024-03-02 12:52:04 -08:00 |
|
Fischer Moseley
|
e2450ddbff
|
complete IO core refactor
|
2024-02-18 15:50:51 -08:00 |
|
Fischer Moseley
|
1528f569ef
|
update submodule usage, tidy logic analyzer config check
|
2024-01-14 12:51:52 -08:00 |
|
Fischer Moseley
|
7a6ab45b92
|
revert UART and InternalBus() refactor
|
2024-01-07 21:39:44 -08:00 |
|
Fischer Moseley
|
bc616fd3bf
|
inital source, imported from splat
|
2023-12-28 14:22:29 -08:00 |