Fischer Moseley
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2c124200da
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docs: autogenerate Python API docs, update IO core docs
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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daedb91ff2
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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3ba93efd2f
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meta: expose Amaranth API via __all__
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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165c6e46ca
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tests: fix logic_analyzer_sim
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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a01b6981e2
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tests: refactor to use Amaranth-native API
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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8fd943257c
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sim: update testbenches to async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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be79ba28b5
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define ABC for cores to inherit from
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2024-03-03 18:53:08 -08:00 |
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Fischer Moseley
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e2d52a6e2d
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add simulate decorator
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2024-03-03 02:14:12 -08:00 |
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Fischer Moseley
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b0dcd269bc
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add from_config to memory_core
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2024-02-19 11:42:28 -08:00 |
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Fischer Moseley
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e2450ddbff
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complete IO core refactor
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2024-02-18 15:50:51 -08:00 |
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Fischer Moseley
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487b11f155
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complete refactor to InternalBus()
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2024-01-07 22:35:15 -08:00 |
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Fischer Moseley
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7a6ab45b92
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revert UART and InternalBus() refactor
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2024-01-07 21:39:44 -08:00 |
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Fischer Moseley
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ee4a3026af
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refactor to use common bus layout across all modules
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2024-01-07 18:17:09 -08:00 |
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Fischer Moseley
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958ccadbd0
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refactored logic analyzer working in sim
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2024-01-05 21:43:53 -08:00 |
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Fischer Moseley
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a11605b2b7
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refactor logic analyzer
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2024-01-05 16:50:25 -08:00 |
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Fischer Moseley
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ee18e10ae1
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add immediate capture mode to logic analyzer
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2024-01-03 13:35:09 -07:00 |
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Fischer Moseley
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bc616fd3bf
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |