Plus: added some missing files
Implementation details:
* scaling factor was introduced in DeviceExtractor::extract
* for easy implementation this is available in "sdbu"
* "sdbu" is made available in GSI
* to test this, the db::compare_netlist had to be enhanced to
exactly check device parameters
* enhancement of LVS script framework and doc updates
- global pins have been generated for device cells too and lead
to implicit pins which may not be desired. The original problem
was how to make abstract circuits comparable. This has to be
solved differently.
- Circuit boundaries are good for displaying the boxes for
abstract circuits
General topic: abstracts and swappable pins.
Issue: we work bottom up and assign pins. This is the
basis for net graph building. But swappable means those
pins can change. The compare works fine, but debugging
output is strange: as the pin assigned is fixed, the nets
found to be attached to a circuit might not fit any
proposed pin pair (which does not contain swapping).
The problem gets worse with abstracts.
The enhancements are
- Such cases generate only warnings in the browser
and the message says swapping might be the case
- Floating nets are treated differently. This should
lead to a better performance for abstracts/black boxes,
but in case of disconnected pins (due to wire errors),
floating nets happen to create mismatches in the nets above.
- Net graph building does not consider swappable nets. In
case of two swappable pins this wouldn't be an issue, but
for more than two this would create ambiguities and
prevent topological matching.
Plus: Debug output option for net graph
Tests updated
Previous: empty layers occupied a special layer in the DSS
But what when empty layers are required as outputs?
ONE layer isn't good -> would overwrite the layer and it's
no longer empty for others.
So we need to keep the layers separate.
So far, duplicate instances have lead to net propagation
into parent cells and floating nets. This is fixed by ignoring
duplicate instances where possible.
- some refactoring
- better performance (was slow because layer iteration
was done outside of loop and recursive cluster iterator)
- with selected nets, only the required hierarchy is
produced. For this a new argument is added to
LayoutToNetlist::create_cell_mapping (nets) which
allows selecting the nets for which a cell mapping
is requested
* Spice writer can now be configure to skip the debug
comments
* < and > are allowed chars in spice names now
* global net names have second prio over labels now
