bad8ed39c1
Parse VHDL subprogram bodies and return statements.
2012-11-03 09:54:07 -07:00
5651e6e001
Improve error handling.
2012-11-02 19:30:12 -07:00
c14134aa2e
Handle genvar variables in expressions.
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In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
2012-09-07 15:14:48 -07:00
85e000ed0c
Handle prefix expressions that include array index expressions.
2012-09-03 16:00:10 -07:00
7fad717a1e
Redesign selected_name rule to better handle complex prefixes
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Prefixes of hierarchical names are complex and cannot be handled
by simple strings, to the rules must be reworked.
2012-09-03 16:00:10 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
4313fbbf1f
Fix space errors in various files
2012-08-16 11:13:32 -07:00
1749d10966
Fix some clang/bison compile warnings.
2012-08-06 15:49:11 -07:00
befff82655
Spelling fixes
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Comments and debug messages.
2012-07-27 18:25:32 -07:00
621c09105c
Sort the typedef emits so that types are emitted in the order used.
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It is common for typedefs of complex types to use further typedefs.
Emit the type definitions depth first so that the types that are used
are defined first. This reduces the need for pre-declaration of types.
2012-05-22 17:31:27 -07:00
369a0b9eca
VHDL named types work in more places.
2012-05-22 17:31:27 -07:00
4748f0cb5e
Handle incomplete type declarations
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Use these in the package library to allow for arbitrary mixing
of type declaration and use. This makes writing libraries much
easier.
2012-05-22 17:31:27 -07:00
039e6014fe
Rework VType::emit_def methods / use packed arrays to implement arrays.
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VHDL arrays are more like SV packed arrays, so use packed arrays
to implement them.
2012-05-22 17:31:26 -07:00
63b7fe059d
Reword concat to handle aggregate arguments.
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When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
67af96fee7
Module output ports use data_type_or_implicit
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This cleans up the parsing of module output ports, allows for more
complex types on the ports, and fixes some bugs.
2012-05-22 17:31:26 -07:00
7e202bb5ca
Fix emit of struct ports/declarations.
2012-05-22 17:31:26 -07:00
71d2401221
Handle VHDL records.
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Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.
While we are at it, handle some cases of array aggregate expressions.
2012-05-22 17:31:26 -07:00
ae06863db1
Elaborate prefix names which may be structure variables.
2012-05-22 17:31:26 -07:00
a5458828cd
Some vhdl parser error handling.
2012-05-22 17:31:26 -07:00
021d944a30
Probe type of ExpName with a record prefix.
2012-05-22 17:31:25 -07:00
7eb89c5548
Parse name prefix syntax for record member reference.
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When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
2012-05-22 17:31:25 -07:00
5e7f61ea42
VHDL process sensitivities go to the end of each iteration
2012-05-22 17:31:25 -07:00
9b816f6478
Add support for nested when/else expressions.
2012-05-22 17:31:25 -07:00
1249b5dd32
Initial support for if_generate syntax.
2012-05-22 17:31:25 -07:00
0775e36a67
Properly elaborate argument types for binary relation expressions.
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The argument types of binary relation expressions are decoupled
from the return type for the expression itself.
2012-05-22 17:31:25 -07:00
ed3da959f3
Support types in packages.
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Types declared in packages should be written into the package library.
2012-05-22 17:31:25 -07:00
79435924f2
Move some VType::show methods to ::write_to_stream methods.
2012-05-22 17:31:25 -07:00
9ed56a6354
Parse record types, and some new aggregate types.
2012-05-22 17:31:25 -07:00
84f14dbc81
Spelling fixes to vhdlpp tree
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Mostly comments as usual, but one error message is changed.
2012-05-17 16:42:03 -07:00
9c99bce054
Update lex/yacc builds to be consistent and to support parallel builds
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Not all the lex/yacc (flex/bison) targets were using a consistent syntax.
This patch fixes that and explicitly serializes the *.c/*.cc and *.h build.
Not doing this was causing problem when using make -j. The issue appears to
be that if two targets are specified for a rule (e.g. file.cc file.h: file.y)
make does not realize they are both built by the same call so the rule is
executed twice. Once for the .cc target and once for the .h target. This is
not a problem for a serial build. To work around this only use the .c/.cc
file in the main target and then make the .h file depend on the .c/.cc file
as a sub-target.
2012-01-04 18:21:40 -08:00
aedbda5a75
Identifiers need to be deleted with delete[]
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This patch fixes a mismatch in the delete style.
2011-12-18 16:45:08 -08:00
ed13de131d
Use mkdir() instead of _mkdir() for MinGW
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MinGW-w64 requires the use of mkdir() and MinGW-w32 appears to support
both so use mkdir() to allow compilation to work with both versions.
2011-12-18 11:43:35 -08:00
8df745a281
Remove SV include file and vhdlpp with make uninstall
2011-12-14 18:39:27 -08:00
cc5efa45ba
Fix two bugs and use the more efficient !empty() vs size() > 0
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These two bugs were found with a recent cppcheck addition. It also
changes one occurrence of size() > 0 for the more efficient ! empty().
2011-11-22 19:44:55 -08:00
bcb963a235
Fix Cygwin compile problem (replace abs() call with ?:
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This patch fixes a compile problem in Cygwin where there are two
definitions for abs() that do not match so the C++ code doesn't know
which one to call. To avoid the whole mess replace the call to abs()
with the appropriate ?: construct.
2011-11-17 14:30:33 -08:00
5e4c0c9783
Merge branch 'master' into work9
2011-11-06 10:27:40 -08:00
8e0beff3ab
Handle arrays of vectors in VHDL types.
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This incidentally adds binding of generic to generic instantation.
2011-11-06 09:01:02 -08:00
c1be255844
Fix dump display of array ranges.
2011-11-05 17:22:30 -07:00
cc508d1626
Support write_to_stream for arithmetic expressions.
2011-11-05 15:55:41 -07:00
2063c5ee9d
Support VHDL user defined array types.
2011-11-05 15:55:17 -07:00
58d182bdf3
Compiler fixes for MinGW.
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In MinGW, when parameters are passed to vhdlpp by ivlpp, single quotes
are treated as ordinary characters. Use double quotes instead, as is
done in the driver.
Also, MinGW does not have a standard mkdir() function, so we need to
convert calls to mkdir() into calls to _mkdir().
2011-11-03 19:11:28 -07:00
98d928f6e0
Add support for VHDL for-generate
2011-10-30 17:10:19 -07:00
5724f71339
Elaborate expressions for entity generics.
2011-10-29 17:07:03 -07:00
15da45f7cb
VHDL initialization expressions for signals.
2011-10-29 17:06:40 -07:00
37ef14b1c8
Implement VHDL conf_std_logic_vector() as SystemVerilog size cast.
2011-10-29 14:47:39 -07:00
4f98a6d181
Rewire VHDL addition expression parsing.
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The VHDL LRM addition expression rules are ... different.
2011-10-23 17:31:58 -07:00
2be682f8a5
Support VHDL component instantiations with generics as Verilog parameters.
2011-10-23 17:08:48 -07:00
eeeadea3ac
Fix recently broken write of vhdl packages to work space.
2011-10-16 12:18:34 -07:00
a109df04bb
Proper expression type for vhdl relation expressions.
2011-10-16 11:02:07 -07:00
93e5a72d84
Get parameter output syntax right for vhdlpp.
2011-10-16 11:01:32 -07:00
Stephen Williams
Arun Persaud
Cary R
Larry Doolittle
Martin Whitaker