bf95d77562
Finish replacing vhdl_process with vhdl_procedural
2008-06-24 20:01:06 +01:00
db992e808f
Start using vhdl_procedural instead of vhdl_process
2008-06-24 19:54:22 +01:00
f2aca68b82
Add new vhdl_procedural superclass for process/task/func
2008-06-24 19:50:57 +01:00
12b448ef01
Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl
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Conflicts:
tgt-vhdl/vhdl_syntax.cc
2008-06-24 19:42:35 +01:00
e77bb0157e
Remove redundant methods from vhdl_arch
2008-06-24 19:39:05 +01:00
75631bd8f1
Move is_inital code out of vhdl_process into vhdl_scope
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Part of tidy up before implementing functions
2008-06-24 19:06:06 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
ba36e47575
Add new vhdl_scope class and refactor
2008-06-24 18:12:00 +01:00
3866c4526e
Simplify code to emit operators
2008-06-24 14:58:58 +01:00
cb08f02de1
Resize signed/unsigned bit vectors correctly
2008-06-24 10:58:21 +01:00
4188fbecee
Add XOR operator and catch default case branch
2008-06-24 10:55:45 +01:00
f261bf7e97
Fix bug where variables could be declared twice
2008-06-23 15:13:10 +01:00
88dc9b6b63
Remove debugging information from the output
2008-06-23 15:02:26 +01:00
632a265e14
Fix casting/resizing order bug
2008-06-23 15:00:55 +01:00
449cd0a76e
Correctly generate signed/unsigned types
2008-06-23 14:28:27 +01:00
181a53d3ed
Merge branch 'master' of git://github.com/steveicarus/iverilog into vhdl
2008-06-23 13:48:56 +01:00
44958409f5
A slightly smarter $display
2008-06-23 13:45:24 +01:00
f81129aa68
Fix some bugs with blocking assignment
2008-06-23 13:36:28 +01:00
e5ef0d97bd
Fix signed/unsigned resizing
2008-06-23 13:04:28 +01:00
469036990a
Output blocking assignments in the right place
2008-06-23 12:30:48 +01:00
d06f5c7c54
Emit loop statements with the correct indent
2008-06-23 12:27:30 +01:00
9911939576
Simplify casting code
2008-06-23 12:21:10 +01:00
c9ace14c40
Shift operators working correctly
2008-06-23 12:14:12 +01:00
d5cdb91d55
Handle complex expressions in case statement
2008-06-23 11:36:12 +01:00
360be597a8
Minor cleanup and comments.
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The initial elaboration needs better comments/documentation.
2008-06-21 18:36:46 -07:00
75f7c9ae0c
Only move constant assignments into initialisation
2008-06-21 16:40:18 +01:00
c926454a41
Statements might be emitted in wrong order
2008-06-21 16:33:05 +01:00
5cfe7ea0aa
Tidy up output
2008-06-21 16:28:07 +01:00
c70fb4ba08
Simple implementation of IVL_EX_SELECT
2008-06-21 16:17:44 +01:00
7cba9f3cb2
Shift left/right
2008-06-21 15:19:33 +01:00
d6acb8d059
Less than / greater than
2008-06-21 15:16:22 +01:00
ec23b70bb7
While loops
2008-06-21 15:13:44 +01:00
58f2f5007d
Bitwise AND
2008-06-21 15:05:48 +01:00
0caf4fd9d0
Add case statement
2008-06-21 15:03:36 +01:00
037ce08f72
Fix tiny bug in $display code
2008-06-21 14:42:54 +01:00
27cdd27889
Add .cast/int and update .cast/real.
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This patch adds .cast/int and updates .cast/real to act as a local
(temporary) net and to support either a signed or unsigned input.
The vvp_vector4_t class not can convert an arbitrarily sized double
to a vector value. This removes the restriction of lround().
Also document the new statements.
2008-06-20 19:45:18 -07:00
f60a6561bb
Cast strlen to int for printf field width
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strlen is a size_t, and the * field width takes an int.
Make this an explicit cast. It's good for 64-bit machines
and squelches warnings from gcc-4.3.
2008-06-20 15:54:32 -07:00
204862ac3c
Implement $write
2008-06-20 19:00:07 +01:00
0f50849fbb
Add call to To_Integer when printing signed/unsigned
2008-06-20 18:26:39 +01:00
404c22ac86
Improved implementation of $display
2008-06-20 11:51:13 +01:00
fe555e4539
Merge branch 'master' of ssh://steve-icarus@icarus.com/~steve-icarus/git/verilog
2008-06-19 21:32:18 -07:00
c87e629150
Better handle nesting of scopes inside generate blocks.
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Within generate schemes it is possible to have nested scopes, even
more liberally then outside generate blocks. So see to it that the
scopes properly stack with the generate blocks, and that wires and
behaviors are put in the right scopes.
2008-06-19 21:31:53 -07:00
b9d6c816f1
Properly evaluate a unary ! with logic argument and real result.
2008-06-19 19:14:19 -07:00
0153a25061
Elaborate nets with real-valued parameters.
2008-06-19 19:13:50 -07:00
476a4c7bc4
Add a script to manually build the version.h file.
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This script is used to manually build a version.h file.
It is needed when building with MinGW using a cygwin
hosted repository.
2008-06-19 16:59:22 -07:00
08d80b35cb
Rename signals that would be illegal VHDL names
2008-06-19 16:15:47 +01:00
6622b5fe3a
Compare logic values for === and !==
2008-06-19 16:08:33 +01:00
d7bb5658f2
Translate IVL_ST_DELAYX statements
2008-06-19 12:16:19 +01:00
2f3627cd6d
Allow generate schemes to generate task/function definitions.
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Generating task/function definitions involves getting the functions
to put themselves into the generate scheme instead of the module,
and getting elaboration to elaborate those definitions in the
generate scheme.
2008-06-18 21:54:58 -07:00
ce9fd0147f
Detect and warn about anachronistic use of begin/end in generate.
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Verilog-2001 only allows a single generate item within a generate-
endgenerate region, but allowed one to collect generate schemes with
begin/end blocks. Verilog-2005 cleaned up that mess, and it is the
2005 syntax that Icarus Verilog implements. This patch detects the
anachronistic use of begin/end within the generate region, ignores
the begin/end words, and prints a warning that the user is using an
obsolete syntax.
2008-06-18 20:33:30 -07:00
Nick Gasson
Stephen Williams
Cary R
Larry Doolittle