Commit Graph

376 Commits

Author SHA1 Message Date
Larry Doolittle f233793061 Spelling fixes
No code changes.
2008-09-09 19:21:42 -07:00
Stephen Williams 4898cd04c6 Remove redundant back-end selections.
Target selection is done by the DLL target code generator, so there
is no value having a layer of target selection ahead of it. Remove
all that redundant code and simplify the target config files to reflect
this.
2008-09-07 16:43:54 -07:00
Nick Gasson 4cb2090978 Fix vhdl_expr::cast when expression has no assigned type
This avoids a couple of segfaults
2008-09-02 20:22:50 +01:00
Nick Gasson ff766899b0 Add IVL_LPM_CMP_GT 2008-09-02 19:07:38 +01:00
Nick Gasson 122890fef4 Make sure LPM expression is cast to the output type
This fixes some signed/unsigned bugs identified by the signedX tests.
2008-09-02 19:02:54 +01:00
Stephen Williams 319b886118 Build files compatible with snapshot 20080830 2008-08-30 17:09:51 -07:00
Nick Gasson 0e458501b3 Ensure binary operands have correct signedness
Previously only signedness was only corrected for the
result. This patch ensures the VHDL operands have the
same signedness as their Verilog counterparts.

This fixes a few of the signedX tests.
2008-08-28 21:53:12 +01:00
Nick Gasson 8323d5d01d Finish cast.cc cleanup
Replace big if statement with switch statemetn
2008-08-27 16:59:05 +01:00
Nick Gasson b5e65ac9ed Refactor and clean up cast.cc
This splits up the monolithic and confusing vhdl_expr::cast function into
several smaller to_XXX functions which each generate code to cast an 
expression to type XXX. This makes it much easier to understand and maintain.
2008-08-27 16:47:07 +01:00
Nick Gasson 8e023d1227 Remove redundant function 2008-08-22 21:27:24 +01:00
Nick Gasson d21b3258e3 Support conversion of (un)signed to std_logic
Take the least-significant bit. This fixes a couple of broken
test cases.
2008-08-22 20:59:14 +01:00
Nick Gasson 331a51e842 Add more warnings about untranslatable constructs 2008-08-22 20:25:58 +01:00
Nick Gasson 63a1e25129 Catch case where component name and instance differ only in case
This causes an error in VHDL (which is case-insensitive). This 
patch simply appends _Inst to the instance name if it detects this.
2008-08-22 20:20:17 +01:00
Nick Gasson fae7ab2418 Use case-insensitive string comparison for get_decl
This will allow us to detect cases where identifiers differ only by case
2008-08-22 20:15:45 +01:00
Nick Gasson 535ef6be38 Change function return value from Verilog_Result to <funcname>_Result 2008-08-21 19:44:12 +01:00
Nick Gasson 4ebe09bb72 Various fixes to support automatic functions
Mostly this ensures that a recursive call to a function
is made with the correct types (this may involve generating
code to cast expressions to the correct type).
2008-08-20 22:54:53 +01:00
Nick Gasson cb1d4fd278 Amend inaccurate comment 2008-08-18 16:15:05 +01:00
Nick Gasson e1deba51ab Handle BUFIF logic when vector inputs 2008-08-18 15:48:07 +01:00
Nick Gasson d53014a07f Fix leading comma it expression only has "others" part
Stop syntax errors caused by things like this:
  (, others => '1')
2008-08-18 15:36:11 +01:00
Nick Gasson 7865264de0 Implement IVL_LPM_REPEAT 2008-08-18 15:34:58 +01:00
Nick Gasson 86661c1538 Add a few more `unsupported' messages 2008-08-18 15:29:30 +01:00
Nick Gasson e2dd7425bd Add error messages for unsupported statement types 2008-08-18 15:24:38 +01:00
Nick Gasson 026d941734 Avoid printing field widths in $display/$write output
This removes some unwanted artifacts from the output.
2008-08-15 19:43:16 +01:00
Nick Gasson a577ee447b Generate process for sequential UDPs 2008-08-13 17:03:03 +01:00
Nick Gasson d7b85c42a0 Split sequential and combinatorial UDPs into separate functions 2008-08-13 11:57:05 +01:00
Nick Gasson dea54df71b Catch possibly NULL return value
This is caused by using a hierarchical reference (which can't
be translated to VHDL). The result of get_decl is NULL since
the signal has been declared in a different VHDL architecture.
Adding the assert is cleaner than having it segfault, for the
moment, until a nicer error message can be added.
2008-08-12 09:47:03 +01:00
Nick Gasson a3929330b0 Fix regression caused by UDP delay patch
translate_time_expr cannot be passed a NULL ivl_expr_t.
2008-08-11 20:53:13 +01:00
Nick Gasson c404b761b7 Change `out' ports to `buffer' when the signal is read
Previously this was handled by creating an internal
signal that was connected to the output and could also
be read inside the entity. The correct solution is to
make the output `buffer' rather than `out'. However, this
does not work in the case when an output is connected to
an output of a child entity, and that values is read
in the parent. In this case *both* the outputs of the child
and the parent need to be made `buffer'.
2008-08-11 20:48:28 +01:00
Nick Gasson 9b1f2d5971 Remove UDP debug messages from output 2008-08-11 20:37:10 +01:00
Nick Gasson 9d7e4ac15f Allow delays in combinatorial UDPs
Add a `after' clause to the `with .. select' statement.
2008-08-11 20:36:09 +01:00
Nick Gasson d55a3a073a Handle '?' in vl_to_vhdl_bit
The rough translation is '-', although the semantics are incompatible
in some cases (e.g. '-' = '1' is false)
2008-08-11 13:53:42 +01:00
Nick Gasson 01bf741983 Implement combinatorial UDPs
Using a `with .. select' statement
2008-08-11 13:23:50 +01:00
Nick Gasson bf3734110e Add VHDL syntax element for `with .. select' statement
This will be used to implement combinatorial UDPs
2008-08-11 13:09:52 +01:00
Nick Gasson 6dcf936807 Generate combined input for UDP devices
Combinatorial UDPs will be implemented with a `with ... select'
statemetnt. However the input to this must be "locally static".
This patch joins the inputs into a vector which can be used as
the select expression.
2008-08-11 12:58:46 +01:00
Nick Gasson 8e0bf3ebff Add conversion from std_logic to (un)signed types
Implemented using the expression (0 => X, others => '0')
2008-08-10 11:22:23 +01:00
Nick Gasson 7ed8c0915d Add file/line comments to signal declarations 2008-08-08 20:28:16 +01:00
Nick Gasson eef1c968dc Add message that casex cannot be translated
...with the correct behavior. It would be possible to
just translate it as a regular VHDL case statement (as
it was before this patch). But the behavior is not
correct as VHDL only does the equivalent of case-equality
in case statements and this can be confusing when debugging
the output. An alternative might be to emit a warning rather
than an error.
2008-08-08 20:09:40 +01:00
Nick Gasson 0985158090 Handle %% in $display 2008-08-08 20:07:22 +01:00
Nick Gasson 090ae5fa56 Catch case where signal with same name in task and module
This fixes task3.14C
2008-08-08 19:47:20 +01:00
Nick Gasson 13cb81f4bb Add task signals to containing architecture
This is necessary to support the in-line expansion of tasks
2008-08-08 19:31:45 +01:00
Nick Gasson bb0efda526 Make make_safe_name case insensitive 2008-08-07 17:58:42 +01:00
Nick Gasson e4d0a92d7c Division and modulus operators 2008-08-07 14:18:26 +01:00
Nick Gasson 28d782e13c Remove redundant verilog_support.vhd file 2008-08-07 13:10:53 +01:00
Nick Gasson 6f5f700cb9 Very minimal implementation of tasks
This expands the task in-line inside the process to avoid
problems with global variables (VHDL processes cannot
reference globals)
2008-08-07 10:54:39 +01:00
Nick Gasson 4cbec1c817 Add XNOR binary operand 2008-08-06 11:18:01 +01:00
Nick Gasson f86f454956 Apply the last patch to if/case statements too
This further cleans up the output by removing more
useless `wait for 0ns' statements.
2008-08-05 11:09:51 +01:00
Nick Gasson e01e038cf9 Avoid generating useless `wait for 0ns' statements
If the final statement in a process is a non-blocking
assignment then there is no point adding a `wait for 0ns'
after it since it will be immediately followed by another
wait. This case is suprisingly common, so this patch helps
generate much cleaner output without breaking the cases
where the 0ns wait is actually required (e.g. to implement
non-blocking assignment properly).
2008-08-05 11:02:36 +01:00
Nick Gasson c849dfeec4 Add XNOR logic device 2008-08-05 10:45:01 +01:00
Nick Gasson 8d7b03576c Correctly implement unary XNOR
Forgot to negate the output.
2008-08-05 10:38:43 +01:00
Nick Gasson 72019959a8 Translate some ternary expressions to if statements
This re-implements some earlier functionality where
ternary expressions on an assignment RHS are translated
to an if statement.
2008-08-03 15:47:32 +01:00