bcb963a235
Fix Cygwin compile problem (replace abs() call with ?:
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This patch fixes a compile problem in Cygwin where there are two
definitions for abs() that do not match so the C++ code doesn't know
which one to call. To avoid the whole mess replace the call to abs()
with the appropriate ?: construct.
2011-11-17 14:30:33 -08:00
5e4c0c9783
Merge branch 'master' into work9
2011-11-06 10:27:40 -08:00
8e0beff3ab
Handle arrays of vectors in VHDL types.
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This incidentally adds binding of generic to generic instantation.
2011-11-06 09:01:02 -08:00
c1be255844
Fix dump display of array ranges.
2011-11-05 17:22:30 -07:00
cc508d1626
Support write_to_stream for arithmetic expressions.
2011-11-05 15:55:41 -07:00
2063c5ee9d
Support VHDL user defined array types.
2011-11-05 15:55:17 -07:00
58d182bdf3
Compiler fixes for MinGW.
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In MinGW, when parameters are passed to vhdlpp by ivlpp, single quotes
are treated as ordinary characters. Use double quotes instead, as is
done in the driver.
Also, MinGW does not have a standard mkdir() function, so we need to
convert calls to mkdir() into calls to _mkdir().
2011-11-03 19:11:28 -07:00
98d928f6e0
Add support for VHDL for-generate
2011-10-30 17:10:19 -07:00
5724f71339
Elaborate expressions for entity generics.
2011-10-29 17:07:03 -07:00
15da45f7cb
VHDL initialization expressions for signals.
2011-10-29 17:06:40 -07:00
37ef14b1c8
Implement VHDL conf_std_logic_vector() as SystemVerilog size cast.
2011-10-29 14:47:39 -07:00
4f98a6d181
Rewire VHDL addition expression parsing.
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The VHDL LRM addition expression rules are ... different.
2011-10-23 17:31:58 -07:00
2be682f8a5
Support VHDL component instantiations with generics as Verilog parameters.
2011-10-23 17:08:48 -07:00
eeeadea3ac
Fix recently broken write of vhdl packages to work space.
2011-10-16 12:18:34 -07:00
a109df04bb
Proper expression type for vhdl relation expressions.
2011-10-16 11:02:07 -07:00
93e5a72d84
Get parameter output syntax right for vhdlpp.
2011-10-16 11:01:32 -07:00
d9acfe57b1
Put off array bound evaluation / describe entity generics as parameters
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Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
a6f63b8a54
Parse generic clause in entity headers
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The generic clause can create named generics in entities. This patch
gets the parser support for them working, even though they cannot
yet evaluate.
2011-10-15 09:49:24 -07:00
209a78a439
Remove a more cppcheck warnings in vhdlpp.
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This patch removes a few more cppcheck warnings in the vhdlpp directory.
2011-10-14 18:40:39 -07:00
8f17e79b7e
Remove a few cppcheck warnings.
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This patch removes a few cppcheck warnings.
2011-10-14 18:40:24 -07:00
6268db6e68
Handle simple type declarations.
2011-10-09 15:25:35 -07:00
30cfcbe2dc
Rework elaborate/emit of types.
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This rework is needed to reasonably handle new types, like enums.
2011-10-02 10:56:00 -07:00
271aaf6376
Parse enumeration type declarations.
2011-10-01 17:04:04 -07:00
8003382b3e
Elaborate and emit case statements.
2011-10-01 11:45:28 -07:00
c59d27e19f
Remove more clang warnings.
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clang warns that the yyinput function generated by flex is never used.
2011-09-25 10:14:16 -07:00
eab5bacf9f
Remove clang/clang++ warnings.
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This patch makes the code consistently use struct/class in the C++ files,
it removes a couple shadow warnings and where a class pointer is passed to
the C routines, it defines the pointer as a class for C++ and as struct for
C and it removes a namespace std duplication.
2011-09-25 10:14:04 -07:00
52019b0e55
Merge branch 'master' into work8
2011-09-18 19:48:50 -07:00
88cce86c63
Emit code for the to_unsigned() bulit-in function.
2011-09-18 19:31:28 -07:00
873a447b5c
Evaluate VHDL <name>'length attribute at compile time.
2011-09-18 17:45:06 -07:00
677a22d353
Generate code for vhdl for loops.
2011-09-18 15:51:31 -07:00
f0e61a1db7
Basic vhdl elaboration for unary not operator.
2011-09-18 15:13:30 -07:00
4d445dc269
Fix parse of unnamed processes.
2011-09-18 09:37:11 -07:00
1d02f89a09
Handle vhdh array aggregate expressions.
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Support the more general case of explicit element expressions
defined at various index positions, mixed with "others" records.
2011-09-11 17:08:22 -07:00
3497e2e663
Distinguish bit selects of entity ports from function calls.
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Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
ca6af1c20d
Fix some space issues.
2011-09-11 11:41:38 -07:00
563d73e7d9
Index/part select of VHDL l-values changes expression type
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The changed expression type impacts how code is generated
for the r-value expression.
2011-09-03 17:57:37 -07:00
6d28c989ce
Handle the basics of aggregate expressions
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This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
2011-09-03 17:11:55 -07:00
4464c5849b
Handle a few built-in functions internally.
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The "unsigned" and "std_logic_vector" functions are internal
functions and VHDL and can be handled internally in the code
generator.
2011-08-28 15:30:45 -07:00
7556a37859
Parse function calls, and detect type case expressions.
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Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.
Also, parse and emit vector part selects.
2011-08-21 16:52:18 -07:00
e6a9b5532a
Report some missed emit error count.
2011-08-21 16:40:06 -07:00
a46c66130b
Emit VHDL symbols as escaped identifiers
2011-08-20 12:11:49 -07:00
78788d17fe
Translate VHDL string literals to bit vectors
2011-08-20 11:11:47 -07:00
13c17a2485
Fix broken creation of ExpString.
2011-08-17 20:53:49 -07:00
f5220c54f1
Handle variables in process statements
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Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
3e3b83da30
Add some detail on how libraries work.
2011-08-05 12:11:54 -07:00
f2629d53a2
Add VHDL support for named libraries
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Named libraries are similar to the work library, but they are not
written to implicitly, or imported implicitly. They are only brought
in by a "library" clause, the the packages within the library are
brought in by a "use" clause.
2011-07-30 15:04:07 -07:00
72769146ee
Remove all the user code compilation warnings
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Remove all the compilation warnings that are from user changeable code.
There are still some warnings related to the flex generated lexor code.
2011-07-30 09:37:14 -07:00
de356b03c8
Fix most of the cppcheck warnings in the vhdlpp directory.
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Mostly using size() vs empty() in the STL and a missing initialization.
2011-07-30 09:35:12 -07:00
836e61e878
Fix spacing issues in the code.
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Remove space at the end of line and space before tab since they serve
no purpose.
2011-07-30 09:33:28 -07:00
547ea61be8
Delete dynamically allocated objects in vhdlpp
2011-07-28 15:03:28 -07:00
Cary R
Stephen Williams
Martin Whitaker
Pawel Szostek