0e458501b3
Ensure binary operands have correct signedness
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Previously only signedness was only corrected for the
result. This patch ensures the VHDL operands have the
same signedness as their Verilog counterparts.
This fixes a few of the signedX tests.
2008-08-28 21:53:12 +01:00
8e023d1227
Remove redundant function
2008-08-22 21:27:24 +01:00
4ebe09bb72
Various fixes to support automatic functions
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Mostly this ensures that a recursive call to a function
is made with the correct types (this may involve generating
code to cast expressions to the correct type).
2008-08-20 22:54:53 +01:00
e4d0a92d7c
Division and modulus operators
2008-08-07 14:18:26 +01:00
4cbec1c817
Add XNOR binary operand
2008-08-06 11:18:01 +01:00
a26d91557b
Add binary NAND and NOR operators
2008-08-01 17:42:26 +01:00
3f73c9bb54
Make sure argument to unary - is signed
2008-08-01 16:35:47 +01:00
09f3eb4a36
Don't bother calling reduction function if argument is std_logic
2008-08-01 16:27:55 +01:00
744fbed783
Finish re-writing nexus code
2008-07-29 19:33:40 +01:00
a842b327c7
Generate constant drivers as concurrent assignments
2008-07-29 14:02:05 +01:00
f8034d69ef
Fix constants in nexuses
2008-07-29 13:30:54 +01:00
506a0ba7d6
Support repeat in concatenation
2008-07-28 21:46:19 +01:00
78028a3310
Fully support ternary expressions
2008-07-28 12:59:10 +01:00
5a09819729
Catch case of select expression on non-variable
2008-07-24 16:00:12 +01:00
e4c2400eb2
Refactor the expression->time code into a single function
2008-07-23 16:18:49 +01:00
a5db0297b0
Unary minus
2008-07-22 15:44:29 +01:00
3ca85491ee
Unary AND and XOR
2008-07-20 16:41:57 +01:00
d8351ec1b2
Fix reduction OR in procedural code
2008-07-20 15:13:20 +01:00
77508b9afa
Reduction OR operator
2008-07-20 15:10:00 +01:00
7b311b6adb
Translate internal delays in assignments
2008-07-18 14:47:35 +01:00
00317dd47f
Dummy implementation of $time
2008-07-18 11:50:05 +01:00
9cf4792d53
Translate array references in expressions
2008-07-17 14:47:10 +01:00
395a2248d8
Make sure 1-bit constants are std_logic not (un)signed
2008-07-16 16:52:15 +01:00
d343db34fd
Fix initialisation order
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Initial processes set a magic flag in the code generator
which allows it to push constant assignments into the
VHDL signal initialisation and omit the assignment.
However, it should only do this if the signal has not
already been read (otherwise the previous read would
not get the undefined value as expected)
2008-07-16 12:00:11 +01:00
0b48f69b4e
Tidy up blocking assignment code
2008-07-15 10:44:48 +01:00
aa951af2b7
Change 'signdness' to 'signdness'
2008-07-10 19:27:17 +01:00
55747bf79d
Refactor signdness changing code into a single function
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This is the code that generated calls to signed/unsigned in
the VHDL output.
2008-07-08 13:07:11 +01:00
1cd7689d03
Fix casting with signed/unsigned expressions
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Previously the code generator tried to infer the VHDL types. Now it
takes a much more dumb approach and forces the VHDL type to be
the same as the ivl type (derived from ivl_expr_signed and
ivl_expr_width) in the expression tree. This works much better :-)
2008-07-08 12:58:50 +01:00
bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
4777966b4c
Bit select bug fixes
2008-07-07 21:19:59 +01:00
47db80315c
Add sign extension LPM
2008-07-07 19:27:52 +01:00
3987e0753d
Fix case where booleans are compared against vectors
2008-07-07 16:31:27 +01:00
4db5b9d7ed
Add unary OR/NOR
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These are currently implemented with reference to an external
Reduce_OR function
2008-07-07 15:23:57 +01:00
bdf5ee7ab7
Concat LPM
2008-07-07 14:48:57 +01:00
ebaa4c7d5d
Implement assignment to part select properly
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Previously the base of the lval was ignored, this ensures
the correct assignment is generated.
2008-07-07 11:00:27 +01:00
c33600bcc3
Add concatenation operator
2008-07-06 18:21:34 +01:00
5aeff6d47d
Merge blocking and non-blocking assignment code
2008-07-04 20:07:38 +01:00
a298b03735
Add bitwise OR
2008-07-04 12:05:49 +01:00
96d32b29c9
Translate logical expressions correctly.
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For logical AND/OR in VHDL both operands must be of the
same type (Boolean)
2008-07-04 11:23:32 +01:00
c54b36c902
Add logical AND operator
2008-07-04 11:10:20 +01:00
6e8474f584
Fix bug where func had to be declared before use
2008-06-30 17:58:15 +01:00
d997397c38
Generate function calls with parameters
2008-06-25 21:49:22 +01:00
44aa8a6b91
Associate signals with scopes rather than entities
2008-06-25 18:12:57 +01:00
a3df37b851
Initial code to generate function calls
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Also catch a few null-pointer issues
2008-06-25 17:29:09 +01:00
e77bb0157e
Remove redundant methods from vhdl_arch
2008-06-24 19:39:05 +01:00
4188fbecee
Add XOR operator and catch default case branch
2008-06-24 10:55:45 +01:00
88dc9b6b63
Remove debugging information from the output
2008-06-23 15:02:26 +01:00
449cd0a76e
Correctly generate signed/unsigned types
2008-06-23 14:28:27 +01:00
e5ef0d97bd
Fix signed/unsigned resizing
2008-06-23 13:04:28 +01:00
9911939576
Simplify casting code
2008-06-23 12:21:10 +01:00
Nick Gasson