Promote the unsigned values to long to get a good comparison and on a
machine where an unsigned is the same size as a long (32 bit) assert
that the unsigned values are constrained to fit into a long. It's unlikely
the values needed to create invalid results would ever happen, but this
patch makes sure it doesn't go undetected.
This is caused by a bug in some simple pattern matching the VHDL target does to try
and produce more idiomatic code in common cases (e.g. FFs with asynchronous resets in
this case). This patch just restricts the kinds of if-statements we use this
optimisation for.
Certain types of expressions involving only constants would produce
ambiguous VHDL output. Fixed by qualifying one of the arguments. E.g.
('0' or '1') = '1'
Which is ambiguous becomes
(std_logic'('0') or '1') = '1'
This fixes the xnor_test test.
Reduce XNOR was implemented incorrectly because of trivial typo
Fixes regression of simple_gen test.
Also extended ivl_lpm_size API call to support all LPM types. This
simplifies some of the VHDL LPM generation code a little.
This patch adds support for running cppcheck from the Makefile. It also
standardizes the order of some of the targets. It renames vpip_format.c
to vpip_format.cc and fixes the size of the array tables to make room
for the trailing NULL. Found when using a C++ compiler.
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
Conflicts:
tgt-vhdl/scope.cc
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Conflicts:
tgt-vhdl/cast.cc
tgt-vhdl/display.cc
tgt-vhdl/vhdl_syntax.cc
tgt-vhdl/vhdl_target.h
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
Conflicts:
tgt-vhdl/process.cc
tgt-vhdl/stmt.cc
tgt-vhdl/vhdl_target.h
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
E.g. $signed(x) > y with x, y different sizes should be
resize(signed(x), N) > y
Not
signed(resize(x, N)) > y
As this does not treat the sign bit correctly. Was causing
the signed5 test to fail.
Martin Whitaker
Maciej Suminski
Christian Taedcke
Cary R
Arun Persaud
Nick Gasson
Larry Doolittle
Stephen Williams