Commit Graph

8365 Commits

Author SHA1 Message Date
Alex Forencich a1ad6d4b51 Support IVERILOG_VPI_MODULE_PATH environment variable 2018-10-28 12:44:09 -07:00
Alex Forencich a638d1eed0 Check for too many paths specified and fix path priority so paths specified on command line supersede built-in paths 2018-10-28 12:43:40 -07:00
Cary R 844fa056f7 Update fstapi files to the latest from GTKWave 2018-10-12 21:30:20 -07:00
Martin Whitaker fdf353af29 Don't use MinGW strtod workaround when building for MinGW-w64.
The host triplet for MinGW-w64 has changed to more closely match that
for MinGW, so we need to update the pattern in the test.
2018-10-07 23:49:19 +01:00
Martin Whitaker 2f142c4858 Revert "Fix x86_64-w64-mingw32 build: undefined ___strtod"
This reverts commit bef04508f2.
2018-10-07 23:47:26 +01:00
Martin Whitaker 9d0d1938dc Fix bug in output of null character with %c format. 2018-10-07 18:59:53 +01:00
Martin Whitaker 5aae9ea770 Fix bit width when converting real value to binary/hex string in VPI. 2018-10-07 17:17:33 +01:00
Martin Whitaker a03995b4da Fix another implicit fallthrough warning. 2018-10-07 11:23:40 +01:00
Martin Whitaker 5cd0ba08b1 Fix alloc size warning when building with recent GCC. 2018-10-06 23:25:13 +01:00
Martin Whitaker 6415d84ed5 Fix invalid cast of TF sizetf callback. 2018-10-06 22:56:04 +01:00
Martin Whitaker 3e25b04685 SIGHUP is not available in Windows. 2018-10-06 21:07:13 +01:00
Martin Whitaker 4ea18196c8 Fix deprecated dynamic exception specification warnings. 2018-10-06 21:02:41 +01:00
Martin Whitaker e71a76a1e2 Fix signed/unsigned comparison warning. 2018-10-06 20:40:54 +01:00
Martin Whitaker 0d20c50de4 Fix typo in last commit. 2018-10-06 20:22:12 +01:00
Martin Whitaker f1608e163f Fix implicit fallthrough warnings when building with recent GCC. 2018-10-06 20:15:42 +01:00
Cary R 27b5c2cdc8 Merge branch 'master' of github.com:steveicarus/iverilog 2018-10-06 09:27:10 -07:00
Cary R 7fa6eaef0a Update to latest GTKWAve files 2018-10-06 09:26:39 -07:00
Martin Whitaker 78317a2799 Fix auto_ptr deprecated warnings when building with recent GCC. 2018-10-06 17:15:31 +01:00
Martin Whitaker 542fe2cf77 Enable checks for VPI const-correctness.
Note we only want these enabled when building the compiler and runtime
binaries. If we included the ICARUS_VPI_CONST definition in the global
CPP_FLAGS, that would propagate to the flags used by iverilog-vpi, so
would affect compilation of user VPI code.
2018-10-06 11:48:19 +01:00
Martin Whitaker 603ff303f5 Cleanly terminate vvp on SIGHUP or SIGTERM (GitHub issue #203). 2018-09-29 23:25:04 +01:00
Martin Whitaker b066a5815e Allow %c format to output null characters (GitHub issue #209)
Currently $display et al. output nothing when the expression
corresponding to a %c format specification has the value 0. As
Verilog provides no other way to write raw bytes to a file, we
should allow 0 values to be written. Other simulators allow this.
2018-09-29 21:22:17 +01:00
Martin Whitaker 0d494da702 Further fixes for const-correctness.
- allow ICARUS_VPI_CONST to be pre-defined by the user
- use it for sizetf as well as for compiletf and calltf
- fix remaining warnings when it is defined as 'const'
2018-09-29 12:04:16 +01:00
Martin Whitaker 8df2f0cadf Fix broken links to SourceForge bug/patch trackers (GitHub issue #207).
Also add link to GitHub issues, as a lot of users report bugs there.
2018-09-28 10:03:06 +01:00
Cary R 3f24557e90 Add some more always_ff synth checks 2018-09-23 22:32:22 -07:00
Cary R e6f957b0b6 Add support for a constant $countbits() function 2018-09-03 15:58:57 -07:00
Cary R 1da9b2cea0 Add support for constant $countones, $isunknown, $onehot, $onehot0 2018-09-03 08:32:41 -07:00
Cary R 2b030ce27a Update the bit vector table name 2018-09-03 08:32:35 -07:00
Cary R b35f9e13c7 Move the bit vector functions to the SV table 2018-09-03 08:32:28 -07:00
Cary R 40558160e7 Add support for bit vector system function in vpi 2018-08-30 22:31:15 -07:00
Cary R ff8ccc0b3e Update fstapi.c to the latest version 2018-07-16 09:03:38 -07:00
Martin Whitaker 11c826216a Fix for GitHub issue #198 - support octal display for thread variables. 2018-06-12 22:58:07 +01:00
Martin Whitaker 7ad5b59a6f Fix for GitHub issue #199: handle signed division overflow.
When performing a signed division or modulus operation using native
arithmetic, trap the special case that the numerator is the minimum
integer value and the denominator is -1, as this gives an undefined
result in C++.
2018-06-12 21:59:58 +01:00
Martin Whitaker 6e49ab10ec Further fix for br1029.
The code in vpi_callback.cc is replicated in vpi_vthr_vector.cc,
so we have to replicate the fix. This should really be factored
out.
2018-05-14 22:14:51 +01:00
Martin Whitaker 87c01c55c0 Don't allow non-vectorable arguments to $signed/$unsigned.
This led to an assertion failure in many cases (see br1029).
1364-2012 indicates it is illegal.
2018-05-14 22:13:56 +01:00
Martin Whitaker 5a4e99b0e8 Fix br1029 - correct rounding when vpi_get_value converts real to integer string. 2018-05-12 23:49:11 +01:00
Stephen Williams 6c39348d1a Merge branch 'master' of github.com:steveicarus/iverilog 2018-04-11 13:40:04 -07:00
Stephen Williams 6c9b3c39b4 Add the --ccflags option to iverilog-vpi 2018-04-11 13:39:53 -07:00
Stephen Williams 797fe44011
Merge pull request #186 from anparks/master
Fixed install step misnomer in README
2018-03-28 12:42:37 -07:00
Aaron Parks fdaf923532 Fixed install step misnomer in README 2018-03-28 12:24:47 -07:00
Stephen Williams 64618af4a9
Merge pull request #123 from dcandrade/master
Added missing compilation instruction on README
2018-03-26 09:55:34 -07:00
Martin Whitaker 5cfb7d68ae Add support for rtran switches in vvp. 2018-02-23 22:30:32 +00:00
Martin Whitaker 36eef5154f Implement supply->strong strength reduction for non-resistive switches.
As specified in 1364-2005 section 7.11.
2018-02-23 22:07:59 +00:00
Martin Whitaker 69d80839a5 Improved check for missing task/function port direction. 2018-02-21 20:07:13 +00:00
Martin Whitaker 6b1b402a79 Fix for br1027: incorrect inference of task/function port direction.
In traditional Verilog, each task_port_item must have an explicit port
direction.

In SystemVerilog, if the port direction is not specified, it should be
inherited from the preceding task_port_item for that task/function, and
only the first task_port_item should infer the direction to be 'input'.
2018-02-20 20:59:26 +00:00
Martin Whitaker f8a2a4816c Enable parameter/localparameter definitions in the compilation unit scope. 2018-02-18 19:21:18 +00:00
Martin Whitaker 2a21fe77ac Output an error message when a SV variable declaration reuses a name.
Assertion failures are not the right way to handle user code errors.
2018-02-18 17:51:56 +00:00
Martin Whitaker caf83b02c1 Enable variable declarations/initialisations in the compilation unit scope. 2018-02-18 14:09:03 +00:00
Martin Whitaker 0f95770418 Include compilation units in pform dump. 2018-02-18 12:53:29 +00:00
Cary R e7a9662b3d A #0 is not allowed in a final block 2018-01-01 21:35:26 -08:00
Cary R 24a4ec3bb2 Hide the always_comb/latch TO event by not attaching it to a scope. 2018-01-01 21:19:58 -08:00