Commit Graph

10199 Commits

Author SHA1 Message Date
أحمد المحمودي (Ahmed El-Mahmoudy) 8de5e68e83 Add CPPFLAGS & LDFLAGS for building version.exe & draw_tt build targets
Those are needed to be able to add security hardening buold flags by
downstream package maintainers
2025-09-28 17:23:40 +02:00
Cary R. d67d3323ad
Merge pull request #1270 from wsnyder/pr1008_finish
Update pr1008.v test to $finish
2025-09-02 07:51:04 -07:00
Wilson Snyder d400fa21bd Update pr1008.v to $finish 2025-09-01 13:41:25 -04:00
Martin Whitaker dad78d5258 Move details of non-standard behaviour from README to Documentation.
Some of this was duplicated in the documentation, some of it was only
in the README. Let's have it all in one place, linked to from the
README.
2025-08-03 18:19:45 +01:00
Martin Whitaker 1be953cfa6 Move documentation of additional system tasks from quirks to extensions. 2025-08-03 17:38:24 +01:00
Martin Whitaker fa5fc0eca0 Copy portability notes from old Wiki to new documentation area.
From https://iverilog.fandom.com/wiki/Verilog_Portability_Notes

Also add formatting tags to $readmempath documentation to make style
consistent.
2025-08-03 17:32:55 +01:00
Martin Whitaker c0e44b4849 Update README to reflect current state of Verilog/SystemVerilog support.
Also
 - remove reference to mingw.txt, which no longer exists
 - extended types are now enabled/disabled by -gxtypes/-gno-xtypes
2025-08-03 15:47:53 +01:00
Cary R db82380cec Minor cppcheck updates in vvp and switch vvp to use override for virtual functions 2025-07-21 23:32:34 -07:00
Cary R 8bd9cb14e7 Cleanup cppcheck suppression file 2025-07-21 23:24:56 -07:00
Cary R 5a4cb616d1 Fix and cleanup tgt-vp based on cppcheck results 2025-07-21 23:21:57 -07:00
Cary R b979441de2 Improve error messages when bad code is passed to the parser 2025-07-21 14:46:56 -07:00
Cary R c7d37bcc21 Error when trying to elaborate a field of a simple variable 2025-07-16 23:37:14 -07:00
Cary R eceb48e5d6 Add better error messages for output port elaboration issues 2025-07-16 22:37:49 -07:00
Cary R e55d9454da Calling front() on an empty() list is undefined 2025-07-13 19:38:43 -07:00
Cary R 30f1de9062 Elaborate input port default value expressions in the correct scope 2025-07-09 09:19:42 -07:00
Cary R cfb8ec17d2 Remove space issues 2025-07-09 07:41:16 -07:00
Martin Whitaker 60e4023e6f Fix log output ordering for vpi_control test when running in Windows.
MSYS2 buffers stderr, so we need to flush the buffers to ensure the
log file matches the gold file.
2025-07-08 22:24:46 +01:00
Martin Whitaker a883f2afe6 Add regression test for vpi_control() return value (issue #1208). 2025-07-08 21:52:13 +01:00
Martin Whitaker 7161dc0ab1 Fix return type of vpi_control() and vpi_sim_control() (issue #1208).
These were implemented as returning nothing (void), and passing an
invalid operation value would trigger an assertion failure. The IEEE
standards define them as returning 1 on success and 0 on failure.

vpi_sim_control() is the name used in Verilog-AMS. Strictly speaking
it should return a bool, but to avoid polluting the namespace by
including stdbool.h, we return a PLI_INT32. As C is a weakly typed
language, this should make no practical difference.
2025-07-08 21:14:49 +01:00
Martin Whitaker fd7029a299 Add regression tests for issue #1258. 2025-07-05 22:52:52 +01:00
Martin Whitaker dd714d78c4 Make -gno-specify suppress unsupported timing check warnings (issue #1258) 2025-07-05 22:44:59 +01:00
Martin Whitaker aec91c7754 Add regression tests for issue #1256. 2025-07-05 18:21:32 +01:00
Martin Whitaker 0ecb71625b Support assignment of parray slices (issue #1256)
The existing elaboration code only allowed assignments from/to individual
elements and either failed an assertion (when assigning the entire array)
or failed to compile (when assigning an array slice).
2025-07-05 18:02:40 +01:00
Cary R f82c6c7b3a Add missing gold and fix VHDL inout test 2025-07-01 00:04:09 -07:00
Cary R 66d57628bf Check what can drive a variable in SystemVerilog 2025-06-30 23:48:26 -07:00
Cary R a05da1ca08 Only synth when the R-value is valid 2025-06-30 16:25:16 -07:00
Cary R 46a5078a68 When optimizing the size of a case keep the sign of the condition 2025-06-25 00:11:22 -07:00
Cary R 6426afc8d0 Avoid overflow in genvar to make duplicate 2025-06-21 18:27:54 -07:00
Cary R a2ffbc307a Validate the generate "loop" expressions 2025-06-21 16:58:30 -07:00
Cary R adcb9f4e0d Add support for passing a real input to logic, mos and if gates 2025-06-21 10:04:12 -07:00
Cary R 26c01e7f0a Use preincrement instead of post in for loop incr 2025-06-20 12:48:01 -07:00
Cary R ea26587b5e The FST dump file is now a fstWriterContext 2025-05-11 22:53:29 -07:00
Cary R 1aec31ac27 Update to the latest FST files from GTKWave 2025-05-11 22:30:40 -07:00
Martin Whitaker b11749e04c Remove Ubuntu 20.04 from workflows as the runner has been retired. 2025-05-11 11:59:04 +01:00
Martin Whitaker b7f9be9370 Add regression test for issue #1242. 2025-05-11 11:39:29 +01:00
Martin Whitaker 2b01cf335c Increment line number when parsing "// synthesis" pragmas (issue #1242)
Thanks to Robert Lance for proposing the fix.
2025-05-11 11:38:28 +01:00
Cary R. 7e238e7ca5
Merge pull request #1229 from AndreasLoow/typo
Typo in `regress-vvp.list`
2025-03-31 13:00:05 -07:00
Andreas Lööw 4138fcf6c4 typo in regress-vvp.list 2025-03-31 08:44:22 +01:00
Lars-Peter Clausen f5decd471d
Merge pull request #1228 from AndreasLoow/typos
Typos in regress-sv.list
2025-03-30 21:03:06 -07:00
Andreas Lööw 7e95dfff5a remove trailing commas 2025-03-30 13:51:44 +01:00
Andreas Lööw bf45073359 typo: nornal -> normal 2025-03-30 13:51:20 +01:00
Cary R b0c57ab177 Update fstapi files to latest from GTKWave 2025-03-12 17:43:38 -07:00
Cary R 99580cd051 Fix warnings that toupper() takes an int 2025-02-17 09:37:18 -08:00
Cary R 6088a26d78 Update VPI example to not have warnings 2025-02-13 01:04:41 -08:00
Cary R 1b729831b7 Cast ispace()/isdigit() args to int to remove warning 2025-02-13 00:03:18 -08:00
Cary R 0ca26c95d8 Cygwin also does not have docopt by default 2025-02-13 00:03:09 -08:00
Cary R 7f4ff37ad0 For cygwin we need to use -std=gnu++11 to get strdup() 2025-02-13 00:02:54 -08:00
Lars-Peter Clausen 14375567c7
Merge pull request #1203 from larsclausen/cast-to-real
Reject invalid casts to real
2025-01-15 19:37:41 -08:00
Lars-Peter Clausen eb90bcf313 Add regression tests for invalid casts to real
Check that invalid casts to real are reported as an error.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2025-01-12 20:34:31 -08:00
Lars-Peter Clausen 4c03ac5b36 Reject invalid casts to real
Only vector types can be cast to real. Report an error when trying to cast
a different type instead of triggering an assert later on.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2025-01-12 19:51:59 -08:00