Commit Graph

5841 Commits

Author SHA1 Message Date
Stephen Williams 8a91931d49 Properly handle base-type logic enumerations.
The next()/prev() methods need to know of the base type
so that the comparisons can go right.
2010-11-21 17:24:46 -08:00
Stephen Williams de215f1f8d Describe enum type to code generators
This gets the enumeration type through to the ivl_target API so
that code generators can do something with it. Generate stub
output with tgt-stub, and generate the proper vvp run time to
make simple enumerations work from end to end.
2010-11-20 15:09:32 -08:00
Stephen Williams 0c72dfe60f Initial implementation of $ivl_method$next/prev
Create the v2009.vpi module to include SystemVerilog core
functions, and start out with some of the enum methods.

Add to vvp support for creating enum types, including some
vpi access methods.
2010-11-17 20:00:23 -08:00
Stephen Williams 00c1176a5d Support enum base type vectors
Including bit/reg/logic types.
2010-11-12 19:28:43 -08:00
Stephen Williams 27dfdf99dd Enumeration element values can be expressions
Allow more complex enumeration expressions, which means putting
off the evaluation of the expression values until elaboration.
2010-11-12 18:47:06 -08:00
Stephen Williams 2f474358d9 Support enumeration element ranges.
This also fixes:
Set verinum.has_sign() correctly for enum values.
2010-11-09 21:05:47 -08:00
Stephen Williams e1344745f8 Handle system functions that return enumerations.
There are a few internal system functions that return enumeration
values, and the type checker needs to properly account for that.
2010-11-07 15:02:42 -08:00
Stephen Williams cc304ef0db Broken implicit enumeration value. 2010-11-07 10:24:04 -08:00
Stephen Williams 5e2c0e5d04 Better handling of width of enum literals in expressions. 2010-11-07 09:58:00 -08:00
Stephen Williams d37126bda5 Implement enum first/last/num methods. 2010-11-05 19:49:28 -07:00
Stephen Williams 5506969882 Little note that IVL_VT_STRING is not support yet. 2010-11-05 18:49:02 -07:00
Stephen Williams cd6c6c7a70 Get the netenum_t base type data from the pform.
The pform propagates the parsed enum base type information
to the elaborator so that the base type can be fully elaborated.
This is necessary to get the types of the enumeration literals
correct.
2010-11-03 20:11:19 -07:00
Stephen Williams 5b5a6b05b7 Test type correctness during elaboration.
Create a netenum_t class to carry the enumeration type in the
netlist.h structures, and use that type to check enumerations
with assignments.
2010-11-02 20:16:42 -07:00
Stephen Williams 94acc39b55 Detect the net.name() method and generate a system function.
SystemVerilog .name() methods can be converted to equivilent
system functions.
2010-10-31 14:07:38 -07:00
Stephen Williams a14fa038b4 Enum names in r-value expressions
When enum names are used as r-values in expressions, use their
values. Treat the enum names similar to (but not exactly as)
localparams so that they fit into the rest of the elaboration
flow naturally.
2010-10-31 11:26:09 -07:00
Stephen Williams cced1e771b Remove some uses of the svector template.
I'm adding more uses of the make_range_from_width function, so
it seems like time to get rid of its use of the svector template.
This thread led to a lot of other uses of svector that had to
also be removed.
2010-10-25 19:36:44 -07:00
Stephen Williams eb4ed82893 Finish up parser code for enum types
This gets the parser syntax actions done, up to the pform code.
It is ready for generating pform structures.
2010-10-24 11:21:17 -07:00
Nick Gasson eba8c8ee65 Fix for pr2661101
Fixes VHDL compilation errors when signal or instance names collide
after renaming.
2010-10-21 19:48:13 -07:00
Stephen Williams 3733c59e49 Merge branch 'work1' 2010-10-21 19:31:49 -07:00
Stephen Williams e5597d5f44 Handle signed IVL_VT_BOOL load into integer.
The %ix/get should be %is/get/s if the source expression is
signed. This gets proper sign extension.
2010-10-21 17:04:56 -07:00
Stephen Williams 9037354c6b reg can take unsigned as well as signed.
SystemVerilog adds "unsigned" so that it can be explicit
as well as implicit.
2010-10-19 19:34:17 -07:00
Stephen Williams b081818a90 Cast expressions from logic to bool.
Handle assignments from logic to bool variables by inserting
the proper cast expression nodes.
2010-10-19 19:09:06 -07:00
Stephen Williams b80dbeee11 Give module port atom2 objects their proper widths.
These widths can be expressions as ranges, but must be present
as this is how we identify them as the various types of ints.
2010-10-19 19:07:44 -07:00
Stephen Williams 162e3aac3a Handle atom2 types in modules input/output ports. 2010-10-18 19:23:02 -07:00
Stephen Williams 9c634e1640 Add a net node for casting to IVL_VT_BOOL values.
BOOL values have a specific cast from LOGIC, this node takes care
of it. Also arrange for the elaboration to insert them in the right
planes and for the code generator to generate them.
2010-10-16 10:53:20 -07:00
Stephen Williams bad1512cb0 The vvp_wire_vec2 class didn't work out.
This class responded badly to inputs that differ only in
zx0 values. It tended to suppress propagations.
2010-10-15 21:01:35 -07:00
Cary R 7dd6883992 The final vvp -Wextra cleanup
This patch resolves the last of the -Wextra warnings by either removing
the parameter or asserting that it is an appropriate value.
2010-10-14 19:18:28 -07:00
Cary R b0269fa926 Add -Wextra for C++ compiling in the vpi and vvp directory.
This patch adds -Wextra to the compilation flags for C++ files in
the vvp and vpi subdirectories. It also fixes all the problems
found while adding -Wextra. This mostly entailed removing some of
the unused arguments, removing the name for others and using the
correct number of initializers.
2010-10-14 19:18:18 -07:00
Cary R be44214598 Add cppcheck target to the Makefile
This patch adds support for running cppcheck from the Makefile. It also
standardizes the order of some of the targets. It renames vpip_format.c
to vpip_format.cc and fixes the size of the array tables to make room
for the trailing NULL. Found when using a C++ compiler.
2010-10-14 19:11:32 -07:00
Cary R 225ee65c31 Fix some vvp initialization problems found with cppcheck.
This patch adds a few missing initializations to various constructors
in the vvp directory. It also enhances the array alias code to copy
more values from the aliased array.
2010-10-14 17:48:12 -07:00
Cary R eb525b6c2a Fix some initialization problem found with cppcheck.
This patch adds a few missing initializations to various constructors
and reworks the realloc() error handling code in driver-vpi/main.c.
2010-10-14 17:48:02 -07:00
Cary R cb86fb15bf Add error checking definitions for malloc(), realloc() and calloc()
This patch adds defines that translate all malloc(), realloc() and calloc()
calls into ones with error checking when ivl_alloc.h is included.
2010-10-14 17:39:23 -07:00
Jared Casper 93f84535b3 Heed and remove warning issued by autoconf 2.68.
Starting in autoconf 2.68, "the macros AC_PREPROC_IFELSE,
AC_COMPILE_IFELSE, AC_LINK_IFELSE, and AC_RUN_IFELSE now warn if the
first argument failed to use AC_LANG_SOURCE or AC_LANG_PROGRAM to
generate the conftest file contents."
2010-10-14 17:35:55 -07:00
Stephen Williams c545cd3e33 Certain expressions can convert BOOL to LOGIC
A ternary can convert BOOL inputs to LOGIC if the select is LOGIC.
A concat is LOGIC if any of its inputs is LOGIC.
2010-10-13 20:07:44 -07:00
Stephen Williams 67000e46a8 Implement atom2 types with vvp_vector2_t.
This reflects the SystemVerilog intent, and also washes away
the 'bx and 'bz values properly.
2010-10-12 20:49:38 -07:00
Stephen Williams 4643872fc6 Generate .net/2x records for IVL_VT_BOOL type nets.
The code generator writes out the proper .net/2x records for
atom2 types, and the vvp run-time parses and interprets those
records.
2010-10-10 19:39:58 -07:00
Stephen Williams ee25f0f217 IVL_VT_BOOL variables generate .var/2x records.
IVL_VT_BOOL variables at the code generator should generate
.var/2x records so that the run time can do 2-value optimizations
and otherwise support atom2 values.
2010-10-10 10:32:19 -07:00
Stephen Williams dd7fecb577 Add missing sv_vpi_user.h header file. 2010-10-10 10:06:27 -07:00
Stephen Williams 568ee4436f Allow variables to implicitly convert to unresolved nets.
SystemVerilog allows variables to be either variables or unresolved
nets, depending on how they are used. If they are assigned by
procedural code, then they are variables. If they are assigned
by a continuous assignment, they are unresolved nets. Note that
they cannot be both, and when they are unresolved nets they can
only be assigned once.
2010-10-10 10:06:27 -07:00
Stephen Williams 6a0cbc5fa8 VPI access to atom2 types.
Create the .var/2u and .var/2s variable records and give them
basic implementations. Make available to VPI the proper types
for the SystemVerilog types that these variables represent.
2010-10-10 10:06:27 -07:00
Stephen Williams af6fd66648 Tasks functions with atom2 arguments.
Parse 2-value atoms as arguments to functions and tasks.
2010-10-10 10:06:27 -07:00
Stephen Williams e03ff763fb Parse support for SystemVerilog atom2 types. 2010-10-10 10:06:26 -07:00
Stephen Williams f7ce0f3b79 Merge branch 'vhdl2'
This is Nick Gassen's work on the VHDL code generator.
2010-10-07 20:59:16 -07:00
Larry Doolittle eaccf4d64f Add possibility of const-correctness
Follow-up to "Brainless start to const-correct changes"
Still actually does nothing, but now if the #define ICARUS_VPI_CONST
in vpi_user.h is changed to const, Icarus is almost const-correct,
as checked with gcc flags -Wcast-qual -Wwrite-strings.

Choosing when to #define ICARUS_VPI_CONST const is left as an
exercise for the reader.

With these two patches applied, and the const define, there are
still about a dozen const problems left.
2010-10-06 15:12:28 -07:00
Larry Doolittle 5d977cac73 Brainless start to const-correct changes
Results of running
cd vpi
for f in *.c *.h; do sed -i \
  -e "s/_calltf(PLI_BYTE8/_calltf(ICARUS_VPI_CONST PLI_BYTE8/" \
  -e "s/_compiletf(PLI_BYTE8/_compiletf(ICARUS_VPI_CONST PLI_BYTE8/" $f; done
and a trivial patch to vpi_user.h to, among other things, make
ICARUS_VPI_CONST blank.

Thus, this patch does absolutely nothing.  Will be followed by a
(much shorter) patch that makes it do something.  :-)
2010-10-06 15:08:54 -07:00
Cary R 3141ef71d0 Add probe_expr_width() for specparam value.
This patch adds a call to probe_expr_width() before a specparam
value is evaluated. This calculates the expression type/width.
2010-10-06 15:04:11 -07:00
Stephen Williams 0950fbb9a3 Clean up some vvp signal casts. 2010-10-06 15:02:45 -07:00
Nick Gasson 0144b5a2bb Basic parameter support in VHDL target
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
2010-10-05 20:03:08 +01:00
Nick Gasson 19b592a336 List parameters/values in VHDL entity comment
For example:

  -- Generated from Verilog module child (vhdl_tests/generics.v:30)
  --   MY_VALUE = 3
  entity child is

To make it clear which values were used for this entity.

Conflicts:

	tgt-vhdl/scope.cc
2010-10-05 20:02:49 +01:00
Nick Gasson 249fc93b89 Change VHDL $finish to use report not assert
Changes:

   assert false report "SIMULATION FINISHED" severity failure;

To just:

   report "SIMULATION FINISHED" severity failure;
2010-10-05 20:02:17 +01:00