884349caab
Two compiler warning fixes.
2025-10-13 19:18:20 +01:00
94dcd658c8
Update exe and manual pages to report @(C) 2025
2025-10-12 19:13:30 -07:00
fcb543d6e5
Some cppcheck cleanup
2025-10-12 17:37:50 -07:00
d79e49a372
Fix compile warning
2025-10-12 17:37:50 -07:00
9c62154924
Fix some new compiler warnings seen when using GCC 15 and clang 21.
...
No functional changes.
2025-10-12 22:23:24 +01:00
4372560290
Post-snapshot cleanup
2025-10-12 11:32:34 +01:00
3e7cc4eac2
Creating snapshot s20251012
2025-10-12 11:32:34 +01:00
cc1ead51c7
Add a define for CC which is used by the iverilog-vpi script
2025-10-11 11:04:54 -07:00
12b87da742
Update config.guess and config.sub to latest versions
2025-10-11 11:02:12 -07:00
fede5239ba
Fix builds using both --enable-suffix and --enable-libvvp options.
...
We need to build libvvp with a suffix from the outset to ensure that
the vvp binary searches for the correct library file name once it is
installed.
Also Windows DLLs need to be stored in the same directory as the main
program, not in a separate lib directory.
2025-10-11 12:03:29 +01:00
23b6f955d4
Fix suffixed vvp build under Windows.
...
Commit 95810b2f61
2025-10-11 10:39:46 +01:00
a4c90fb5f0
Add regression test for issue #1273 .
2025-10-07 21:54:11 +01:00
936f92ebe6
vvp: demangle identifiers when parsing the input file (issue #1273 ).
...
The tgt-vvp code generatpr outputs identifiers as quoted strings, and
because of this, escapes any " and \ characters (which may appear in
escaped indentifiers). We need to undo this when reading them into
vvp, so that the original name is seen by the VPI routines.
2025-10-07 21:53:11 +01:00
1fdeb7b982
Add regression tests for $fmonitor tasks.
...
Also add a test for multiple $monitor task calls and $monitoron and
$monitoroff.
2025-10-05 12:37:30 +01:00
753a52b56c
Add support for $fmonitor tasks (issue #1280 )
2025-10-05 12:34:25 +01:00
d67d3323ad
Merge pull request #1270 from wsnyder/pr1008_finish
...
Update pr1008.v test to $finish
2025-09-02 07:51:04 -07:00
d400fa21bd
Update pr1008.v to $finish
2025-09-01 13:41:25 -04:00
dad78d5258
Move details of non-standard behaviour from README to Documentation.
...
Some of this was duplicated in the documentation, some of it was only
in the README. Let's have it all in one place, linked to from the
README.
2025-08-03 18:19:45 +01:00
1be953cfa6
Move documentation of additional system tasks from quirks to extensions.
2025-08-03 17:38:24 +01:00
fa5fc0eca0
Copy portability notes from old Wiki to new documentation area.
...
From https://iverilog.fandom.com/wiki/Verilog_Portability_Notes
Also add formatting tags to $readmempath documentation to make style
consistent.
2025-08-03 17:32:55 +01:00
c0e44b4849
Update README to reflect current state of Verilog/SystemVerilog support.
...
Also
- remove reference to mingw.txt, which no longer exists
- extended types are now enabled/disabled by -gxtypes/-gno-xtypes
2025-08-03 15:47:53 +01:00
db82380cec
Minor cppcheck updates in vvp and switch vvp to use override for virtual functions
2025-07-21 23:32:34 -07:00
8bd9cb14e7
Cleanup cppcheck suppression file
2025-07-21 23:24:56 -07:00
5a4cb616d1
Fix and cleanup tgt-vp based on cppcheck results
2025-07-21 23:21:57 -07:00
b979441de2
Improve error messages when bad code is passed to the parser
2025-07-21 14:46:56 -07:00
c7d37bcc21
Error when trying to elaborate a field of a simple variable
2025-07-16 23:37:14 -07:00
eceb48e5d6
Add better error messages for output port elaboration issues
2025-07-16 22:37:49 -07:00
e55d9454da
Calling front() on an empty() list is undefined
2025-07-13 19:38:43 -07:00
30f1de9062
Elaborate input port default value expressions in the correct scope
2025-07-09 09:19:42 -07:00
cfb8ec17d2
Remove space issues
2025-07-09 07:41:16 -07:00
60e4023e6f
Fix log output ordering for vpi_control test when running in Windows.
...
MSYS2 buffers stderr, so we need to flush the buffers to ensure the
log file matches the gold file.
2025-07-08 22:24:46 +01:00
a883f2afe6
Add regression test for vpi_control() return value (issue #1208 ).
2025-07-08 21:52:13 +01:00
7161dc0ab1
Fix return type of vpi_control() and vpi_sim_control() (issue #1208 ).
...
These were implemented as returning nothing (void), and passing an
invalid operation value would trigger an assertion failure. The IEEE
standards define them as returning 1 on success and 0 on failure.
vpi_sim_control() is the name used in Verilog-AMS. Strictly speaking
it should return a bool, but to avoid polluting the namespace by
including stdbool.h, we return a PLI_INT32. As C is a weakly typed
language, this should make no practical difference.
2025-07-08 21:14:49 +01:00
fd7029a299
Add regression tests for issue #1258 .
2025-07-05 22:52:52 +01:00
dd714d78c4
Make -gno-specify suppress unsupported timing check warnings (issue #1258 )
2025-07-05 22:44:59 +01:00
aec91c7754
Add regression tests for issue #1256 .
2025-07-05 18:21:32 +01:00
0ecb71625b
Support assignment of parray slices (issue #1256 )
...
The existing elaboration code only allowed assignments from/to individual
elements and either failed an assertion (when assigning the entire array)
or failed to compile (when assigning an array slice).
2025-07-05 18:02:40 +01:00
f82c6c7b3a
Add missing gold and fix VHDL inout test
2025-07-01 00:04:09 -07:00
66d57628bf
Check what can drive a variable in SystemVerilog
2025-06-30 23:48:26 -07:00
a05da1ca08
Only synth when the R-value is valid
2025-06-30 16:25:16 -07:00
46a5078a68
When optimizing the size of a case keep the sign of the condition
2025-06-25 00:11:22 -07:00
6426afc8d0
Avoid overflow in genvar to make duplicate
2025-06-21 18:27:54 -07:00
a2ffbc307a
Validate the generate "loop" expressions
2025-06-21 16:58:30 -07:00
adcb9f4e0d
Add support for passing a real input to logic, mos and if gates
2025-06-21 10:04:12 -07:00
26c01e7f0a
Use preincrement instead of post in for loop incr
2025-06-20 12:48:01 -07:00
ea26587b5e
The FST dump file is now a fstWriterContext
2025-05-11 22:53:29 -07:00
1aec31ac27
Update to the latest FST files from GTKWave
2025-05-11 22:30:40 -07:00
b11749e04c
Remove Ubuntu 20.04 from workflows as the runner has been retired.
2025-05-11 11:59:04 +01:00
b7f9be9370
Add regression test for issue #1242 .
2025-05-11 11:39:29 +01:00
2b01cf335c
Increment line number when parsing "// synthesis" pragmas (issue #1242 )
...
Thanks to Robert Lance for proposing the fix.
2025-05-11 11:38:28 +01:00
Martin Whitaker
Cary R
Wilson Snyder