Commit Graph

6240 Commits

Author SHA1 Message Date
Cary R fa759c1802 Fix problem with delay at t0 when only some of the bits change.
This patch makes sure the delay is calculated correctly when only some
of the bits change and you are comparing against the initial (t0) value.
Basically you have to check the initial value against all the bits in
the new signal not just the first bit since the order that bits change
is not deterministic.
2008-01-31 16:42:51 -08:00
Cary R 4c5481f254 Add delays for shifts, concatenation and replication in a CA.
This patch add delays in continuous assignments for the shift operators,
concatenations and replications. It also reports an error if the user
attempts to take the modulus of a real value.

This patch uncovers a couple other problems in the system. I am trying
to fix one of them. I will report the other problem shortly.
2008-01-31 16:39:12 -08:00
Cary R 1609de6ed9 Fix some bit based delays in continuous assignments.
This patch fixes some of the delays in bit based continuous
assignments (unary -, unary +constants, string constants,
reduction operators and user functions).

Use draw_lpm_output_delay() in all functions that need it.
2008-01-29 20:27:53 -08:00
Larry Doolittle d9ac146b8f Spelling fixes
only comments and documentation
some punctuation and capitalization for good measure
Changelogs are purposefully untouched
2008-01-29 20:24:24 -08:00
Larry Doolittle 31afec57b1 Fix for pr1879226, large constant shift values
Addresses pr1879226 on a couple of levels.  Analysis:

NetNet* PEBinary::elaborate_net_shift_() didn't flag dist==lwidth
as a case where all bits of the input are shifted away, which made
it create a real concatenator for this case.  It attempted to create
NetNet*tmp with zero width, which doesn't work; (lsb,msb) ends up
as (0,-1), which is later interpreted as a 2-bit wide net.

Added an assert to the NetNet constructor to catch any other lurking
attempts to create zero-width nets.

Added short-circuit code to handle the case where all bits of the input
are shifted away.  This case used to be "handled" by an assert failure.
2008-01-29 09:31:16 -08:00
Stephen Williams 76039cf595 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2008-01-28 21:33:14 -08:00
Stephen Williams 685095b229 Support delay of user function output
When used in continuous assignments, user defined functions may have
delayed output. Handle that by generating the proper .delay node when
needed to delay the output of a .ufunc node.
2008-01-28 21:29:03 -08:00
Stephen Williams abfccb65e9 User defined functions take real arguments
Allow user defined functions to take real value arguments and return
real value results in net contexts. Use the data type of the nets
attached to the ports to define the data types of the arguments and
return value.
2008-01-28 18:57:55 -08:00
Larry Doolittle 388bb93beb Spelling fixes
only comments and documentation
2008-01-28 09:15:39 -08:00
Stephen Williams 1eb581ab37 Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2008-01-28 09:13:33 -08:00
Stephen Williams 2f9ad47890 Merge branch 'master' of steve-icarus@icarus.com:git/verilog 2008-01-27 18:25:11 -08:00
Larry Doolittle 47d65034db Spelling fixes
mostly comments, but includes some identifiers and message text
2008-01-27 18:18:13 -08:00
Stephen Williams b297a0a9fe Remove support for vvp32 build
Remove configure and Makefile support for the vvp32 build. Remove
also the libdir64 support.
2008-01-25 17:33:32 -08:00
Larry Doolittle 6256dd8040 Add support for ivl debug flags. 2008-01-25 11:16:44 -08:00
Stephen Williams 5ec91ec914 Add datarootdir to makefiles
It seems that later versions of autoconf expect datarootdir to be
use and set.
2008-01-24 12:10:31 -08:00
Stephen Williams 76164d7711 Rework compile-time evaluation of LT and GT
There was much redundant code in the compile-tile handling of the
less-then and greater-then of constant expressions, and much of it
was buggy. Unify much of the code and squeeze out the bugs so that
compile-time evaluations come out correctly.
2008-01-23 20:43:13 -08:00
Stephen Williams 89bf16b21e Signed-ness of parameters
Propagate the signedness of named parameters when they are evaluated.
2008-01-22 20:16:43 -08:00
Stephen Williams 5b17f2039a Fix bug in eval of <= compare
The compiler attempts to precalculate the results of <= comparisons.
Fix a few corner cases where the arguments are signed. Also fix the
important test of constant against non-constant where we try to test
if the non-constant value can possibly make the test fail.
2008-01-21 22:05:50 -08:00
Stephen Williams db25bba0d0 Fix assertion fail handling certain conditional delays
When conditional delays are in use, it is sometimes possible for there
to be no delays available for a given input event. In that case, skip
the delay processing for that case instead of crashing.
2008-01-21 19:57:17 -08:00
Cary R 10d25d2b88 Support delays for all operators in a continuous assignments.
Previously only the logical operators (~, &, |, ^, etc.) supported a
delayed value in a continuous assignment. This patch should extend this
to all operators. An extensive check of real values was done. The same
will be done shortly for bit based nets.

Checks for constructs currently unsupported in continuous assignments
provide a more explicit message (** operator, real user functions,
{!, && and ||} operators with a real argument).
2008-01-21 18:21:31 -08:00
Stephen Williams 3ea72109f8 Read and include sign of scanned decimal.
Fix simple bug where negative values read from the source file were
not getting their sign. The fix was proposed in pr1876738.
2008-01-21 18:11:28 -08:00
Stephen Williams b6b7d704b2 Clean up lexing of net literals.
The matching of net literals (i.e. Cx<> and T<> symbols) should not get
in the way of properly matching other symbols.
2008-01-21 17:52:40 -08:00
Stephen Williams 32d3e5ac46 Better formatting of Cr<> label for real valued drivers.
Rework the encoding of a real value in the Cr<> label to be similar to
the format used by the %loadi/wr instruction. This mantissa-expoment
format better carries all the bits of the desired real value with
plenty of fidelity and range.
2008-01-19 16:27:09 -08:00
Cary R ea1f448300 Real multiply in a cont. assign. is always 1 bit wide.
The continuous assignment multiply expands vectors to the sum
of the two widths. This is correct for bit based vectors, but
for real variables it should always be one bit wide.
2008-01-17 12:52:30 -08:00
Stephen Williams d992ec4bd4 Declare $rtoi in system.sft instead of the sys_funcs table.
The sys_funcs table should be left to those functions that are handled
internally by the compiler. Really, the internal sys_funcs table is a
legacy from the days before the compiler supported system function
tables in the .sft format.
2008-01-17 12:48:02 -08:00
Cary R 592a303ce5 Add $rtoi to system func. table and add check for NULL name.
System functions used in a continuous assignment must be defined
in the system function table since the name of the system functions
is kept in this definition. The default name is NULL which causes
problems. This patch add $rtoi to the system table and adds a check
for a NULL name.
2008-01-17 12:42:05 -08:00
Cary R 52a346ab38 Print real constant value comment with %g
The comment that shows the intended value for real constants was
being printed with a %f. This is wrong for large or small values.
This patch changes the %f to a %g to get more consistent results.
2008-01-17 12:31:08 -08:00
Cary R 0fa223434e Add check target to tgt-verilog/Makefile.in
Add the missing check target to Makefile.in.
2008-01-17 12:29:15 -08:00
Stephen Williams e1bf2ec019 Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2008-01-16 16:55:26 -08:00
Cary R ded0fbe5ef Fix user functions with right shift argument.
A right shift may generate extra bits to preserve the proper shift
characteristic. This patch replaces the assert that was forcing the
input vector to not be greater than the input port width with code
to only select the required lower bits from the vector if it is
larger than the input port.
2008-01-15 21:01:16 -08:00
Cary R 0370f30b20 Support variable delay of a variable selected assignment.
This patch adds support for the following statement:

<vector>[<i>] <= #<delay> <value>.

It is a copy with slight modification of code from the next
else/if clause.
2008-01-15 20:33:36 -08:00
Cary R eac6333d6c Add missing deletes for patch "Add real compar..."
Add two deletes that I missed in the previous patch.
2008-01-15 19:48:49 -08:00
Cary R 1ff31db2cc Add real comparisons in continuous assignments.
This patch adds real comparisons in continuous assignments.
It also converts bit based constants to real values when needed
by the comparisons.
2008-01-15 19:48:26 -08:00
Stephen Williams 59ee700634 Net arrays that are addressed are not dangling
The nodangle functor tries to delete NetNet objects that are not used.
But NetNet objects that are addressed by a NetArrayDq should never be
dangling. So make sure the NetArrayDq marks the target NetNet correctly.
2008-01-15 19:39:53 -08:00
Cary R e46f8220f3 Evaluate non-immediate signal selection.
This patch adds code to treat non-immediate signal selection the
same as the default logic evaluation
2008-01-14 19:55:14 -08:00
Cary R 7ff342f4da Fix type warning in tgt-vvp/eval_expr.c
In a previous patch I missed this type inconsistency.
2008-01-14 19:51:38 -08:00
Stephen Williams 190aefcf89 Use inttypes.h to get uint64_t print format string
Code generators should not include _pli_types.h to get standard int
types and strings. Use the inttypes.h header file instead.
2008-01-14 09:53:20 -08:00
Stephen Williams cdfe3a8289 Use inttypes.h to get uint64_t print format string
Code generators should not include _pli_types.h to get standard int
types and strings. Use the inttypes.h header file instead.
2008-01-14 09:47:48 -08:00
Cary R c899a6a52e Add %load/avp0 opcode and fix %load/vp0.
This patch adds a new opcode %load/avp0 that is used to load a
word from an array and add a value to it. %load/vp0 was
changed/fixed to do the summation at the result width not the
vector width. This allows small vectors to index large arrays with
an offset. A few errors in the opcodes.txt file were also fixed.
2008-01-13 19:47:49 -08:00
Cary R e18b64768e Add missing check target in some Makefile.in files.
This patch adds a check target to the Makefile.in files in the
tgt-null, tgt-stub and vpi directories.
2008-01-11 21:52:51 -08:00
Cary R 7157a68d08 Edge-control does not require conditional event
This patch allows the edge control to be used without a
conditional event.
2008-01-11 14:24:52 -08:00
Larry Doolittle e03fd9e6f2 fix leftover signed/unsigned comparisons
triggers warnings in gcc-3.3.5 and gcc-3.4.6 vintage compilers
2008-01-11 14:16:21 -08:00
Stephen Williams 731f1df70b Hook up input port part select properly.
The input part select that is used to match a module port to a short
vector connected to it was wired incorrectly.
2008-01-10 20:47:06 -08:00
Stephen Williams 9d0cdc8ae9 Hook up output port part select properly.
The output part select that is used to match a module port to a long
vector connected to it was wired incorrectly.
2008-01-10 18:20:21 -08:00
Stephen Williams f944d31353 Improved assertion on signal arrays.
Use ivl_expr_file() information to improve a signal assert message.
2008-01-09 14:24:30 -08:00
Stephen Williams 6cc8d0e536 Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2008-01-09 11:03:40 -08:00
Stephen Williams 3b89c1767c Merge branch 'pr1864110' 2008-01-08 18:56:12 -08:00
Stephen Williams 1f7957c612 Fix type handling of real-value system functions in nets
In nets, if system functions return a real value the function lookup
was getting the correct width, but was also setting the width to 0,
which confused down-stream net handling. Real-value system fuctions
have a width of 1. (1 real-valued scalar.)
2008-01-08 18:54:55 -08:00
Larry Doolittle eb5e7b792b Spelling fixes
Sorry, I can't help myself.  :-p
2008-01-08 17:26:55 -08:00
Stephen Williams 1db3c75ce6 Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog 2008-01-08 17:16:38 -08:00