6902bf44e3
Improved error handling in parser around typedefs.
2014-02-16 17:04:52 -08:00
8f849a9944
Sorry message for unpacked array module ports.
2014-02-16 15:56:32 -08:00
b1ef0997ed
Merge branch 'x-sizer3'
2014-02-15 15:19:55 -08:00
ecce1d25bc
Fix for GitHub issue 12 : Ternary lval-rval width mismatch.
...
A simple typing error that caused the expression to be incorrectly
evaluated as a real constant.
2014-02-15 23:05:41 +00:00
f43080fbcb
Detect proper support for missing else_ without latches (synthesis)
2014-02-15 14:54:58 -08:00
463407572f
Sizer pay attention to ivl_synthesis_off attribute.
2014-02-15 14:44:55 -08:00
6b6574dd8a
sizer support for simple LPM MUX devices.
2014-02-15 14:44:15 -08:00
4e81939eda
Handle asynchronous if-without-else synthesis.
2014-02-15 14:16:22 -08:00
66bdbb77ec
Fix for GitHub issue 9 part 2 : Efficiency of the verinum pow() function.
...
This changes the verinum pow() function to use the more efficient algorithm
used in the vvp runtime. It will still be slow if the left operand is unsized
and the right operand is large, as it will expand the result vector to avoid
overflow.
2014-02-15 22:06:31 +00:00
5853f7d867
Fix for GitHub issue 9 part 1 : Efficiency of vvp_vector2_t::pow() function.
...
The vvp_vector2_t::pow() function is recursive, and performs a multiplication
operation on each step. The multiplication operator was expanding the result
vector to accomodate the maximum possible result value for the given operand
vectors, thus causing the execution time of the power operation to be
exponentially proportional to the exponent value. Both in this case and
in general, it is unnecessary for the multiplication result vector to be
expanded, as the compiler has already determined the required vector width
during elaboration, and sizes the operand vectors to match.
2014-02-15 21:40:55 +00:00
68f8de28af
Fix for GitHub issue 7 : Undef propagation in power operator.
...
The vvp_vector2_t constructor that takes a vvp_vector4_t value was
documented as creating a NaN value if the supplied vector contained
any X or Z bits, but instead used the standard Verilog 4-state to
2-state conversion semantics (X or Z translate to 0). I've added an
optional second parameter to the constructor to allow the user to
choose which semantics they want, as both are needed.
2014-02-15 13:14:45 +00:00
ac3aee0172
Fix for GitHub issue 8 : Signedness of constant binary bitwise operations.
...
When doing constant evaluation of binary bitwise operations, the result
value must be signed if the expression type is signed.
2014-02-15 11:39:05 +00:00
8135f369a5
Fix for GitHub issue 11 : Syntax error on operator attributes.
...
Attributes are allowed to be attached to unary, binary, and ternary
operators in expressions. For now just accept and discard them.
2014-02-14 23:29:22 +00:00
be5bfeb172
Elaborate widths of parameters correctly for unsigned values
...
If there is no size in the parameter type declaration or on the
value itself, then give the parameter value a minimum width of
integer bits.
2014-02-11 18:24:12 -08:00
801e795112
Better job of matching adder operand sizes for vec4 code generator.
2014-02-10 18:06:56 -08:00
e66fc7e5cc
Port UWIRE assignments to vec4 branch.
2014-02-10 17:19:52 -08:00
1d63875e5d
Merge branch 'master' into vec4-stack
...
Conflicts:
elab_lval.cc
2014-02-10 16:26:22 -08:00
be1130ddbf
More robust case statement synthesis
...
Handle the cases that the case statement carries complet sub-
statements. This is just a generalization of what is already
there.
2014-02-09 17:30:30 -08:00
9f2b7d6553
Rearrange counters to me more realistic
...
Instead of counting gate types, convert to gate count estimates
and some other interesting statistics. Also handling the descent
into child scopes.
2014-02-09 08:59:51 -08:00
f5041e6c09
Collect some actual sizer statistics.
2014-02-08 18:53:42 -08:00
959ac3229e
Start a sizer backend.
2014-02-08 10:16:11 -08:00
554fb7ebdd
Various internal vec4 size mismatches fixed.
2014-02-07 17:50:13 -08:00
c9e8392dc7
Fix dangling vec4 stack when force assignment is suppressed.
...
Also improve the %debug/thr instruction.
2014-02-07 16:10:28 -08:00
60d37e1f53
More vec4 support for various things.
2014-02-07 11:24:41 -08:00
e0ac4893f0
Fixed homepage link
...
The link was pointing to a page that said:
This page has been moved to http://iverilog.icarus.com , you will be forwarded there automatically in 3 seconds.
Please update your links.
So now it's updated
2014-02-07 12:22:53 +00:00
401fccdf6e
vec4 handling of DARRAY of vec4 vectors.
2014-02-06 15:05:26 -08:00
f5564a195f
vec4 versions of compressed assignment statements.
2014-02-06 09:55:25 -08:00
c7e61f3aa4
Merge branch 'master' into vec4-stack
2014-02-05 15:18:25 -08:00
a012406ca4
Fix broken search where member names accidentally match variables.
2014-02-03 20:04:24 -08:00
52a9fdde8a
Handle packed structs as module outputs.
2014-02-03 19:22:59 -08:00
4f1c43b690
Account for force l-values that are uwires.
2014-02-02 17:05:42 -08:00
7f59c51ca2
Handle proceedural writes to UWIRE objects.
...
The elaborator allows this only if it determines that the bits
that are procedural written are not also continuously written.
2014-02-02 16:43:48 -08:00
0be577cc44
Allow some behavioral assignments to unresolved wires.
...
If the l-value is an unresolved wire, then elaboration can allow
the assignment as long as it is to bits that are not otherwise
driven. Handle this in some simple cases.
2014-02-02 11:08:43 -08:00
49cf5556a2
Fix primitive table lexical analysis.
...
Sequences of digits in the table of a primitive may be matched
as decimal numbers instead of digits, and this breaks some
primitives.
2014-02-02 10:57:53 -08:00
1805598eae
Fix some vec4 handling of putc, len, and other string methods.
2014-01-31 19:01:28 -08:00
0eca210722
Merge branch 'master' into vec4-stack
2014-01-30 17:07:54 -08:00
3e95966d70
More spelling fixes
...
Mostly comments
Changs "initilzers" in a string visible with debug_elaborate.
Includes a few British->American changes in the root directory only.
2014-01-30 16:43:17 -08:00
fdc9e8590d
Merge branch 'master' into vec4-stack
2014-01-30 15:59:51 -08:00
f76d56beb8
Remove lint detected by clang
...
With this change, iverilog builds and runs with no extra warnings when using clang 3.0
2014-01-30 15:39:55 -08:00
be17bfc0e9
Spelling fixes
...
Mostly comments.
One user-visible string ("Evalutated to ") changed in the debug_eval_tree case.
2014-01-30 15:34:20 -08:00
77a01f65d0
Remove fixable unused-parameter warnings
...
I see other warnings within vhdlpp/lexor.cc caused by a flex bug
(see http://sourceforge.net/p/flex/bugs/115/ ), which I won't try to work around.
2014-01-30 15:34:08 -08:00
e497f63e29
Implement string compares for vec4 support.
2014-01-28 17:11:21 -08:00
75233a9bca
vec4 implementation of auto-increment/decrement.
2014-01-28 16:24:26 -08:00
11197baf86
The vec4 %cvt/vr requires a <wid>
2014-01-28 15:51:29 -08:00
23ba0bc019
various vec4 fixes.
2014-01-25 19:25:21 -08:00
9cfb15a302
Implement assign/vec4/off/e
2014-01-23 18:39:29 -08:00
607b63a758
Merge pull request #5 from cliffordwolf/master
...
Added missing support for binary ^~ in eval_tree.cc
2014-01-23 17:12:05 -08:00
8bebe59e20
Fix vec4 abs() generating duplicat labels.
2014-01-22 17:15:26 -08:00
20d415463a
vec4 non-blocking assign to array swapped delay and part offset!
2014-01-21 20:58:48 -08:00
9c1dcad994
vec4 vvp support for non-blocking assign with delay and part offset.
2014-01-21 19:37:05 -08:00
Stephen Williams
Martin Whitaker
Colin
Larry Doolittle