49a2693357
Add file / line number information to functions
2008-08-03 14:46:57 +01:00
10a5ca199d
Add file / line number comments to instantiations
2008-08-03 14:38:08 +01:00
c2f622327f
Use ivl_scope_def_* for definition file/line numbers
2008-08-03 14:34:41 +01:00
45dfa28dba
Remember signal pin a nexus was attached to
...
Also modify nexus_to_var_ref to set the correct array
offset when the signal is an array (the offset comes
from the pin).
2008-08-03 11:41:26 +01:00
c8cbac58f5
Add forward declarations for functions
...
This patch adds a forward declaration for every user funciton.
This fixes VHDL compile problems if a function calls another
before it has been declared.
2008-08-03 10:50:31 +01:00
5d0df8d880
Change format of line file/line numbers
2008-08-02 10:42:00 +01:00
bb80b432e6
Add comments file/line number comments
...
Added to entities, architectures, and processes
2008-08-01 21:21:42 +01:00
baa2363e85
Split logic device code into separate file
2008-07-30 10:13:08 +01:00
e5b8abfb23
Remove debugging output
2008-07-29 21:15:51 +01:00
9a5b7bb0b0
Connect signals together if joined in a nexus
2008-07-29 21:03:00 +01:00
eaf1cc9120
Fix assertion failure with arrayed signals
2008-07-29 19:47:17 +01:00
3bcd42dc8f
Fix case where logic device has no valid output
2008-07-29 19:39:20 +01:00
744fbed783
Finish re-writing nexus code
2008-07-29 19:33:40 +01:00
c9454b346e
Fix module3.12B
2008-07-29 19:04:41 +01:00
5ec2c37e7e
Get functions working again
2008-07-29 15:29:49 +01:00
25602e487d
Comment
2008-07-29 15:12:51 +01:00
e037ffd952
Create temporaries for LPM outputs
2008-07-29 15:09:58 +01:00
48c1a7982c
Make seen_nexus private
2008-07-29 14:24:04 +01:00
a842b327c7
Generate constant drivers as concurrent assignments
2008-07-29 14:02:05 +01:00
f8034d69ef
Fix constants in nexuses
2008-07-29 13:30:54 +01:00
680c6f0503
Make sure LPMs have valid inputs/outputs
2008-07-29 13:06:21 +01:00
39717989a8
Call set_active_entity in the right places
2008-07-29 13:04:29 +01:00
c26b7ce675
Port maps
2008-07-29 13:02:55 +01:00
c6f6ea7358
Instantiation working again
2008-07-29 12:21:19 +01:00
c0c838f1bc
Logic devices now working again
2008-07-29 12:11:44 +01:00
1a45e9164f
Find signal a logic device is connected to
2008-07-29 12:04:40 +01:00
8a5f129e56
Draw nexus in multiple passes
2008-07-29 12:00:26 +01:00
65c2ceb89d
Build entity hierarchy in separate stages
2008-07-29 11:01:02 +01:00
e4c2400eb2
Refactor the expression->time code into a single function
2008-07-23 16:18:49 +01:00
30fdadc525
Support delays in logic devices
2008-07-23 13:40:42 +01:00
2d79e1a2e0
Store the currently active entity
2008-07-19 14:45:00 +01:00
4d9f029000
Generate correct array bounds
2008-07-17 14:38:07 +01:00
1d3ac6bc1f
Generate VHDL array type declarations of Verilog arrays
2008-07-17 13:08:55 +01:00
c116808fdb
Remove duplicated code
2008-07-17 11:46:36 +01:00
642fbe9fc5
Correct check for arrays
2008-07-17 11:31:06 +01:00
f3753ea9ad
Add warning that arrays are not yet implemented
2008-07-15 18:09:18 +01:00
b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
f84f50842c
Support bufif for tri1 nets
2008-07-14 19:13:11 +01:00
65720f49fe
Simple bufif cases
2008-07-14 19:00:58 +01:00
6243736481
Pull-up/pull-down logic devices
2008-07-14 12:04:20 +01:00
e331e4831b
Fix nexus_to_expr where nexus has IVL_LPM_SELECT_PV
2008-07-14 11:53:38 +01:00
78ee61558d
Remove redundant test
...
Signal is guaranteed to appear in arch_scope or its parent
by the surrounding `if' statement.
2008-07-13 15:27:07 +01:00
07c4ff7ea7
Add assertion about result of lpm_to_expr
2008-07-13 15:26:03 +01:00
e5422dddd2
Remove useless `ignore' param to nexus_to_expr
2008-07-13 15:24:35 +01:00
6af201ea03
Refactor nexus expansion functions.
...
Now a single function nexus_to_expr
2008-07-13 15:17:14 +01:00
27a40cfdcd
Constant assignments to outputs
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If the Verilog source contained a continuous assignment
of a constant to an output, it would not be present in
the VHDL output. This patch generates a VHDL continous
assignment in these cases.
2008-07-13 13:02:17 +01:00
3bd480a375
Allow ouput to be read if connected to child output
...
If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
2008-07-13 12:41:02 +01:00
bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
860a74ddd8
Allow LPMs in port maps
2008-07-07 20:41:29 +01:00
47db80315c
Add sign extension LPM
2008-07-07 19:27:52 +01:00
Nick Gasson