5f90a3e48c
Translate sub-statement of @{..}
2008-06-06 18:22:03 +01:00
96cf190720
Generate signals and sensitivity list for @(..) statement
2008-06-06 17:56:52 +01:00
373832ba22
Specify correct sensitivity list
2008-06-06 17:36:15 +01:00
4f472e451e
Stubs for statement types in mux2.v test
2008-06-06 16:55:45 +01:00
d36bbec5b5
Generate VHDL for no-op statements
2008-06-05 13:16:35 +01:00
e258058cf1
Fully qualify std.textio.Output to avoid name collisions
2008-06-04 21:58:51 +01:00
c3ac1aac8c
Remove debugging messages from output
2008-06-04 21:07:50 +01:00
234f73e7bf
Don't generate any output if there were errors
2008-06-04 21:03:36 +01:00
f49dd97d24
Add support for blocks and make hello1.v test pass
2008-06-04 20:57:15 +01:00
7bd1565cfb
$display now (mostly) working
2008-06-04 20:42:44 +01:00
6e448da90d
Emit Write() calls for parameters of $display
2008-06-04 15:19:44 +01:00
9f035108e1
Stub code for translating expressions
2008-06-04 14:59:04 +01:00
4bf2e1669d
Store packages required with entity rather than globally
...
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
2008-06-04 13:52:56 +01:00
dd30c1b39d
Support procedure call generation for $display
2008-06-04 13:27:42 +01:00
94006cb44c
Working on code generation for $display task
2008-06-03 19:46:10 +01:00
2e6ec91ce0
Scalar types
2008-06-03 19:20:45 +01:00
fe80da362c
Collect required packages as compilation progresses
2008-06-03 19:14:47 +01:00
82aca1b02e
Stub code for handling $display
2008-06-03 18:44:17 +01:00
4211e651d0
Stub file for processing statements
2008-06-03 18:26:36 +01:00
f9e1289463
Tidy up vhdl_element.cc
2008-06-03 17:43:54 +01:00
a09b4e3b92
Initial process have wait at the end
...
(do it properly this time rather than a hack :-)
2008-06-03 17:39:24 +01:00
ab6ae621cb
Remove useless comments in output
2008-06-02 20:24:25 +01:00
17ae0a6a09
Fix a bug where the same instantiation appeared multiple times
2008-06-02 18:05:39 +01:00
041925c123
Component instantiation to replicate Verilog hierarchy
2008-06-02 17:45:58 +01:00
9292a087e8
Generate VHDL processes from Verilog processes
2008-06-02 16:17:01 +01:00
fef0fd82ff
Comments
2008-06-02 00:12:47 +01:00
5cbd587833
Clean up generated objects
2008-05-31 16:08:57 +01:00
7c9d154461
Forgot source files for entity generation
2008-05-31 15:31:48 +01:00
8189c4ee43
Generate VHDL entities and architectures for all module scopes
2008-05-31 15:28:25 +01:00
05de2f56b4
Dummy code for processes
2008-05-30 01:04:47 +01:00
e38494a10c
Pretty-print VHDL output
2008-05-29 16:24:16 +01:00
e178baefbd
Merge branch 'master' of git://github.com/steveicarus/iverilog into vhdl
2008-05-28 17:23:12 +01:00
bfa2bfc8ae
Makefile and autoconf changes to build VHDL code generator
2008-05-28 17:17:39 +01:00
2179797763
Do not allow unknows to be handled as logic immediate.
2008-05-27 19:48:31 -07:00
b5e9e44e07
Fix error in of_SUBI with wide results.
...
This patch fixes an error in the recent rework of of_SUBI.
It was doing a double bit inversion.
2008-05-27 19:42:20 -07:00
5a0fe9ff83
Better use of immediate operands.
...
Clarify that operands are typically 32bits, and have the code generator
make better use of this.
Also improve the %movi implementation to work well with marger vectors.
Add the %andi instruction to use immediate operands.
2008-05-27 17:51:28 -07:00
f6fede5aae
Merge branch 'master' of ssh://steve-icarus@icarus.com/home/u/icarus/steve/git/verilog
2008-05-27 11:55:45 -07:00
0fa3099ded
Optimize %div and %div/s
...
Use high radix long division to take advantage of the divide hardware
of the host computer. It looks brute force at first glance, but since
it is using the optimized arithmetic of the host processor, it is much
faster then implementing "fast" algorithms the hard way.
2008-05-27 11:54:39 -07:00
6987d16bd3
Optimize the %load/vp0 to use subarrays.
...
This instruction adds an integer value to the value being loaded. This
optimization uses subarrays instead of the += operator. This is faster
because the value is best loaded into the vector as a subarray anyhow.
2008-05-26 16:44:58 -07:00
5cc376ebd4
Optimize ADD and MUL instructions
...
Make better use of the CPU word in ADD and MUL instructions.
2008-05-26 16:00:16 -07:00
8190307dd3
Optimize/inline vvp_bit4_r AND, OR and vector set bit.
...
The AND and OR operators for vvp_bit4_t are slightly tweaked to be
lighter and inlinable.
The vvp_vector4_t::set_bit is optimized to do less silly mask fiddling.
2008-05-26 11:09:33 -07:00
3575f68c9f
Merge branch 'master' into verilog-ams
2008-05-23 21:23:16 -07:00
c1268d04fc
Merge branch 'verilog-ams' of ssh://steve-icarus@icarus.com/~steve-icarus/git/verilog into verilog-ams
...
Conflicts:
ivl_target.h
t-dll.h
2008-05-23 20:55:46 -07:00
ca756f3ec3
Bring switch information out to the ivl_target API.
...
This involves defining the API for switches and cleaning up the
elaborated form to match the defined ivl_target API. Also add t-dll
code to support the ivl_switch_t functions, and add stub code that
checks the results.
2008-05-23 20:53:10 -07:00
9af459f95b
Vectorize AND/OR/NAND/NOR/INV instructions when reasonable.
...
When processing wide vectors of these operations, it pays to process
them as vectors. This improves run-time performance. Have the run time
select vectorized or not based on the vector width.
2008-05-23 17:52:43 -07:00
492b240304
Optimize vvp_vector4 vector handling.
...
Improve vvp_vector4_t methods copy_bits and the part selecting constructor
to make better use of vector words. Eliminate bit-by-bit processing by
these methods to take advantage of host processor words.
Improve vthread_bits_to_vector to use these improved methods and Update
the %load/av and %set/v instructions to take advantage of these changes.
2008-05-23 14:30:32 -07:00
d2106a3d3a
Fix botched processing of MUX with constant select.
...
If the select input was constant, the code then tried to look at the
constant data input. Just plain wrong.
2008-05-23 10:29:44 -07:00
cf2f4dd0af
Merge branch 'master' of ssh://steve-icarus@icarus.com/~steve-icarus/git/verilog
2008-05-22 20:36:18 -07:00
608c2574bd
Add $finish_and_return.
...
This new system task can be used to set the vvp return value
and finish the simulation.
2008-05-22 20:34:38 -07:00
f17db21bf0
Make sure stringify_flag is always initialized.
...
Put in one last initialization of stringify_flag,
that Cary missed in add84b153c73dcace781
2008-05-22 20:32:26 -07:00
Nick Gasson
Stephen Williams
Cary R
Larry Doolittle