Otherwise it is not possible to modify their values in subprograms.
Argument elaboration has been moved to a separate function, so now it is
common for procedure and function calls.
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
Build up a work library by writing a VHDL representation of the
package header into a source file. This representation needs to
be accurate enough that later invocations of vhdlpp can read them
with the VHDL parser.
Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
Significant rework of scope management to unify the handling of
types in the ieee library and types/constants/components in packages.
This involved adjusting the parser rules to manage a stack of scopes
and rewriting the IEEE library support to not use global maps for
the loaded types.
Make sure in a conponent instantiation that the instantiated
component is really declared, and that the ports of the binding
really do match the ports of the declared component. This requires
that we create and save component declarations, and that components
have methods for mapping the ports.
There has been added additional default attribute to
all 'dump' function calls which is in all cases equal
to 0. Now one can specify how much this debug dumping should
be intended. This should allow people to dump smoothly whole
designs (as it was now) as far as separate units.
This is now the parent who specifies the base indentation
for all components (children). For example, architecture
"decides" how much their signals should be indented.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.
Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
Rather then leave net types to implicit declarations, write
declarations explicitly. This will become necessary when more
interesting types are supported.
Separate elaboration from code generation in the Entity, and add
to Architectures a code generator to handle some simple cases. At
this point we have the basic structure for the VHDL compiler.
Include the compiler infrastructure to vhdlpp for collecting the
file and line information and attaching it to entities and ports.
Make the parser store the file name during parse.
Create a libmisc library where I can put source files that are
used by multiple programs within the source tree.
Martin Whitaker
Maciej Suminski
Christian Taedcke
Cary R
Arun Persaud
Larry Doolittle
Stephen Williams
Pawel Szostek