luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
5,629 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

5422 Commits

Author SHA1 Message Date
Alan Mishchenko ae2e3f90f7 Adding command &genmux. 2024-07-11 22:23:06 -07:00
Alan Mishchenko 13998baf97 Allowing the genlib reader to skip gates larger than the given size. 2024-07-10 12:59:10 -07:00
Robert O'Callahan 6c6260465e Make `lbool` explicitly signed 
This avoids issues due to some platforms making `char` signed and others
unsigned. For example, currently the result of promoting `(lbool)-1` to `int`
can differ on different platforms. See
50ffa10848/lib/bill/bill/sat/interface/abc_bsat2.hpp (L156)
for an example of that.
 2024-06-28 01:07:10 +00:00
Alan Mishchenko 2d70debd07 Corner-case bug fix. 2024-06-18 23:01:03 +08:00
alanminko 7beda11621
Merge pull request #302 from mikesinouye/scl 
Change Scl_Pair_t_ membes to long to enable larger liberty file loading.
 2024-06-17 10:12:12 +02:00
Alan Mishchenko 24d420370a Adding switch "i" in "show" to display original AIG IDs of mapped nodes. 2024-06-16 17:49:39 +08:00
Mike Inouye a6bf51111f Change Scl_Pair_t_ member types to long to allow for large liberty file loading. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-06-13 23:12:45 +00:00
Alan Mishchenko 806a996b88 Updating the print-out after the bug fix. 2024-05-30 08:43:58 +02:00
Alan Mishchenko 17b1ec7655 Bug fix. 2024-05-29 22:05:40 +02:00
Alan Mishchenko fb4988bb13 New API to print internal nodes. 2024-05-28 22:23:07 +02:00
Xiaoqing Xu 34c2ed73a2 up stream changes 2024-05-23 22:51:15 +00:00
Alan Mishchenko 795fee8d57 Bug fix in &genrel. 2024-05-23 13:51:10 -07:00
Alan Mishchenko 23f351c7c6 Bug fix in word-level abstraction. 2024-05-23 07:47:30 -07:00
Alan Mishchenko 111867432c Compilation problem. 2024-05-21 10:26:01 -07:00
Alan Mishchenko 0cb945ebcd Enabling support of boxes in &nf. 2024-05-21 10:15:46 -07:00
Alan Mishchenko 8ec95e85c6 Bug fix. 2024-05-19 15:03:12 -07:00
Alan Mishchenko c64f927828 Various changes and bug fixes. 2024-05-19 14:47:18 -07:00
Alan Mishchenko 3616fd8fb5 New command "resub_unate" and various changes. 2024-05-17 02:56:33 -07:00
Alan Mishchenko 3fd42912ad Suggested fix. 2024-05-16 06:24:18 -07:00
Alan Mishchenko 5fc62b881f Code to dump resub instances. 2024-05-15 22:21:22 -07:00
Alan Mishchenko d9a08eb44b New command &window to extract windows from an AIG. 2024-05-15 21:41:29 -07:00
Alan Mishchenko 2c02ae89a0 Updating the previous commit. 2024-05-15 09:41:14 -07:00
Alan Mishchenko c906dfb748 Upgrading "twoexact" to read relations in an updated format. 2024-05-15 09:33:57 -07:00
Alan Mishchenko 6ad6539c0f New command &genrel to generate relations for windows in the AIG. 2024-05-14 22:35:43 -07:00
Alan Mishchenko daf3313ce6 New aliases. 2024-05-13 23:31:50 -07:00
Alan Mishchenko 554da94ea6 New command &odc to study observability don't-cares. 2024-05-13 22:59:11 -07:00
Alan Mishchenko 66c7f67b96 New command "resub_core". 2024-05-13 21:31:28 -07:00
Alan Mishchenko f04f9c4353 Updating counter-example generation. 2024-05-08 23:45:14 -07:00
Alan Mishchenko c194c112ae New way to generate counter-examples. 2024-05-08 23:13:31 -07:00
Alan Mishchenko 3c56ccb8fb Add warning when trying to CEC AIGs with xor-gates. 2024-05-08 08:15:45 -07:00
alanminko ae92ea0214
Merge pull request #297 from aletempiac/yosys-flow 
Integrating delay-driven LUT decomposition in &if
 2024-05-07 06:43:53 -07:00
aletempiac d109372fb7 Adding delay-driven LUT decomposition to &if 2024-05-07 11:03:24 +02:00
Alan Mishchenko fb97997991 New command &putontop to create large AIGs. 2024-05-04 13:38:32 -07:00
Ethan Mahintorabi 246337cdbe
Fixes incorrect extern definition of Wlc_BlastMultiplier3 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-03 01:55:31 +00:00
aletempiac 5708841672 Merge remote-tracking branch 'origin/master' into yosys-flow 2024-05-02 10:23:16 +02:00
aletempiac 714ab458b7 Adding deriving LUTs to if 2024-05-02 10:23:11 +02:00
aletempiac 39ed8b36d4 Cleaning code 2024-05-02 10:06:40 +02:00
Ethan Mahintorabi b7c7a6d98d
Fixes duplicate declaration of Abc_SclHasDelayInfo 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-02 02:15:59 +00:00
William D. Jones 402c2579db Modify include guards in cmd.c so that Windows compilers don't compile Unix-only code. 2024-04-27 19:06:36 -04:00
aletempiac 043a2ffcc6 Adding new XX decomposition to &if 2024-04-23 11:10:16 +02:00
Alan Mishchenko c14d5f3906 Dumping miter statistics. 2024-04-22 22:06:07 -04:00
Martin Povišer e6a3dc602c Fix prototype mismatch for `Gia_ManSimRsb` 2024-04-22 17:34:38 +02:00
aletempiac 864f96b11e Adding decomposition of mapping into LUT structures before returning the result 2024-04-16 17:40:47 +02:00
Peter Gadfort de060a26ad ensure initial library writing also honors prefix 2024-04-16 08:58:28 -04:00
Alan Mishchenko bc725b85de Bug fix in CNF generation for &glucose (three more places). 2024-04-15 20:29:38 -07:00
Alan Mishchenko 2d6b5c9adc Bug fix in CNF generation for &glucose. 2024-04-15 20:25:43 -07:00
Alan Mishchenko 99e0e37da6 Added switch -p in "read_lib" to skip writing cell prefix. 2024-04-14 09:51:00 -07:00
Peter Gadfort 935c6a875d add missing flag to read_lib help 2024-04-12 13:49:44 -04:00
Peter Gadfort 1d90cafd54 add library merging flag to read_lib 
Signed-off-by: Peter Gadfort <gadfort@zeroasic.com>
 2024-04-12 13:27:58 -04:00
aletempiac 045803dcb8 Merge remote-tracking branch 'origin/master' into acd66 2024-04-11 19:02:29 +02:00
aletempiac 0c905f873b Fixes 2024-04-11 19:01:05 +02:00
aletempiac 6052d10fde Adding new command if -U for 2-LUT decompositions under delay profile 2024-04-11 15:45:37 +02:00
aletempiac e8924e5534 Fixes and improvements 2024-04-11 15:44:52 +02:00
aletempiac 5b49724fcc removing acd666 2024-04-11 15:43:22 +02:00
Alan Mishchenko ca78f5e6e5 Bug fix in the resub engine. 2024-04-11 05:05:52 -07:00
aletempiac 32bc1d4ab2 Cleaning and generalizing code 2024-04-11 11:31:28 +02:00
aletempiac 64fea5c4c2 Improving the performance and quality of acd66 2024-04-10 18:43:52 +02:00
aletempiac 6b5ebb3e76 Removing assertion when decomposing into LUTs smaller than 6 2024-04-10 18:42:52 +02:00
aletempiac 8f3447800c Support again decompositions into luts smaller than 6 2024-04-02 11:25:03 +02:00
Alan Mishchenko 6e1653426f Switch to randomly select one choice. 2024-03-28 16:22:06 +08:00
Alan Mishchenko a2cb5eb4e3 Adding command &pms to print miter status. 2024-03-25 23:39:03 +08:00
aletempiac 1f72ffce79 Improving ACD performance with bail-out conditions 2024-03-25 14:23:43 +01:00
Alan Mishchenko b0d2ff1c63 Exact synthesis using NAND-gates. 2024-03-24 00:10:08 +09:00
aletempiac 6aacf524aa Performance improvement and fixes 2024-03-22 19:19:35 +01:00
aletempiac 8a314db8dc Bug fix 2024-03-22 15:39:52 +01:00
Alan Mishchenko 2c0943ff62 Fixiing compiler problem on Windows. 2024-03-19 09:34:20 +09:00
Alan Mishchenko 5d3d77fcfe Fixing Windows compiler problem. 2024-03-19 08:54:32 +09:00
Alan Mishchenko c32f36af08 Fixing c vs c++ header file issue. 2024-03-19 08:13:07 +09:00
Alan Mishchenko b31ab1960b Fixing compilation issues on Windows. 2024-03-18 21:30:46 +09:00
aletempiac db72df7a63 Merge remote-tracking branch 'origin/master' into acd66 2024-03-18 10:08:48 +01:00
aletempiac 3737a69d8d Adding new ACD66 with support for multiple shared-set variables 2024-03-18 10:01:59 +01:00
Alan Mishchenko 210474b08c Bug fix in &gen_hie. 2024-03-18 07:49:35 +09:00
alanminko 3040b8ddd5
Merge pull request #282 from allen1236/master 
&brecover with speculative reduction
 2024-03-16 08:52:57 +09:00
Allen Ho b7884aaf2b clean up & add options for &brecover 2024-03-16 01:40:11 +08:00
Allen Ho 015dd2a367 use speculative in &brecover 2024-03-15 16:56:10 +08:00
Alan Mishchenko a16a0f1027 Writing Verilog for AIG using NAND gates. 2024-03-06 01:40:48 -08:00
Allen Ho d87b1cd543 fixed some warnings in bsat2 2024-03-04 10:16:14 +08:00
Allen Ho bfbec71211 &stc_eco and &brecover done 2024-03-04 09:36:35 +08:00
Allen Ho bcf04fadb6 &brecover done 2024-03-04 00:54:23 +08:00
Alan Mishchenko a747f46292 More changes to compile with g++. 2024-03-02 17:21:05 -08:00
Alan Mishchenko eb24d29777 More changes. 2024-03-02 17:10:30 -08:00
Alan Mishchenko b73f1030a6 More changes. 2024-03-02 17:03:42 -08:00
Alan Mishchenko b627aa7cb5 More changes. 2024-03-02 16:57:00 -08:00
Alan Mishchenko ce44eda85a More changes. 2024-03-02 16:46:09 -08:00
Alan Mishchenko f6f542c873 More changes to compile with namespaces. 2024-03-02 16:38:16 -08:00
Alan Mishchenko 4de4605836 More changees to compile new code with namespaces. 2024-03-02 16:31:41 -08:00
Alan Mishchenko a1159d98df Fixing a compiler problem with namespaces. 2024-03-02 16:10:37 -08:00
alanminko 390a0e8ef3
Merge pull request #279 from allen1236/master 
Sat-sweeping-based ECO (&str_eco)
 2024-03-02 15:38:08 -08:00
Allen Ho 23654254e1 clean up 2024-03-03 03:06:13 +08:00
Allen Ho f5f4dca013 clean up 2024-03-02 21:08:10 +08:00
aletempiac cd407e2ba3 Activate use_first flag in acd_decompose 2024-03-01 10:05:30 +01:00
aletempiac 9bec2afd60 Removing -z flag to execute delay-driven ACD 2024-03-01 10:04:48 +01:00
Allen Ho 6f5656c188 shared EI/EO not handled yet 2024-03-01 16:05:41 +08:00
Alan Mishchenko 1fd79c8430 Fixing a bug in input/output name ordering. 2024-02-29 15:19:47 -08:00
aletempiac fa8a277765 Changing search space exploration of ACD to search for better implementation and prune unnecessary computations based on theoretical properties 2024-02-29 17:16:49 +01:00
aletempiac 48b5f3b399 ACD66 performance improvements by avoiding unnecessary computation 2024-02-29 17:15:29 +01:00
aletempiac 75abcd376b Adding bindings to use ACD66 instead of generic ACD 2024-02-28 09:51:32 +01:00
aletempiac 44a65c23ed Adding relaxation on the maximum free set constraint 2024-02-27 17:47:43 +01:00
aletempiac d3f140f1df Performance improvements 2024-02-27 17:36:24 +01:00
aletempiac f72000f5ae Adding ACD cascade 666, performance improvements 2024-02-21 18:25:48 +01:00
aletempiac eba56b088f Cleaning code and performance improvements 2024-02-21 17:13:29 +01:00
aletempiac 13fd0d55c7 Removing unnecessary structs 2024-02-21 09:47:16 +01:00
aletempiac 0cd548f1cb Performance improvements to ACD 2024-02-20 17:28:50 +01:00
aletempiac 0e471e3ff8 Performance improvements of ACD 66 2024-02-20 14:41:52 +01:00
aletempiac 7b74810047 Changing policy of finding ACD 66 decomposition (faster and 100 percent coverage) 2024-02-16 16:43:24 +01:00
aletempiac 17afd93c78 Extending ACD to work up to 11 variables 2024-02-08 15:36:09 +01:00
aletempiac 3f80b202cd C++11 compatible code 2024-02-08 14:57:42 +01:00
aletempiac 2afaeac823 Adding hash table to reduce computations 2024-02-08 11:20:19 +01:00
aletempiac 2d9af6c9a4 Adding ACD for 66 LUT structure using a new method 2024-02-08 09:36:58 +01:00
Alan Mishchenko 52e0a10bf7 Fixing a compiler problem. 2024-02-05 20:49:36 -08:00
Alan Mishchenko e9a0bf6bf9 Adding reversing of simulation bits in &sim_read. 2024-02-05 20:32:11 -08:00
Alan Mishchenko d7ef3cc030 Bug fix in &fx. 2024-02-05 19:29:50 -08:00
Alan Mishchenko 62a22c7574 Bug fix in blasting multipliers with different argument bit-width. 2024-02-05 19:26:36 -08:00
Allen Ho c74144c6eb str_eco ver1 2024-02-01 07:25:46 +08:00
Alan Mishchenko 6d1d52deaa Adding an option to read the RTL elaboration library from the current directory. 2024-01-30 20:22:55 -08:00
Alan Mishchenko d6555f48dd Adding a switch to not write the timestamp in the AIGER file. 2024-01-26 07:31:20 -08:00
Alan Mishchenko 5fa9192412 Change how &stochsyn runs on a single core. 2024-01-18 18:34:50 -08:00
Alan Mishchenko 8da884de85 Switch to reverse the order of bits. 2024-01-18 18:23:11 -08:00
Baruch Sterin 234af64a8c Workaround for C++17 compilation (on clang) 2024-01-18 09:58:18 -08:00
Baruch Sterin d140535d64 Adapt previous merge by @aletempiac to compile with ABC namespaces. 2024-01-17 15:04:31 -08:00
aletempiac d223898f3d Merge remote-tracking branch 'origin/master' into acd 2024-01-16 17:44:45 +01:00
aletempiac 67aab70cff Moving ACD package to if folder 2024-01-16 17:42:43 +01:00
Alan Mishchenko 5bc99574fc Eliminating dependency on "abc.rc" in "&deepsyn". 2024-01-12 22:54:44 -08:00
aletempiac 38e632a954 Consider buffers in matrix covering as free 2024-01-12 14:50:34 +01:00
Alan Mishchenko 8c7327b8df Recognizing interface of the module when writing Verilog. 2024-01-11 22:19:50 -08:00
Alan Mishchenko dc68fe27f9 Saving module interface. 2024-01-11 19:45:42 -08:00
aletempiac 7dcc10a254 Minor fixes 2024-01-10 15:18:39 +01:00
alanminko 7f0a319564
Merge pull request #269 from rmlarsen/speedup_scanning 
Micro-optimizations to speed up the Liberty parser by ~1.67x.
 2023-12-21 12:58:42 +09:00
Alan Mishchenko 5978ccdb52 Updating sleep command to wait for file. 2023-12-21 12:16:33 +09:00
Rasmus Munk Larsen 706112ebd8 Micro-optimizations to speed up the Liberty parser by ~1.67x. 
Signed-off-by: Rasmus Munk Larsen <rmlarsen@google.com>
 2023-12-19 16:13:52 -08:00
Alan Mishchenko 7fe92148cc New command to put computation to sleep. 2023-12-18 21:04:31 +09:00
Allen Ho 284b9d6a9c extended box report; 2023-12-10 21:30:46 +08:00
Alan Mishchenko 16a3c5fc30 Add copying names in &saveaig and &loadaig. 2023-12-09 21:53:48 +08:00
Allen Ho 9bb5333f62 extend bo 2023-12-07 19:07:52 +08:00
aletempiac b3d2419d9a Formatting, renaming, and cleaning code 2023-11-27 13:38:36 +01:00
aletempiac 6097fd4349 Code formatting 2023-11-24 14:24:20 +01:00
aletempiac 23cfcc1e1f Improving efficiency and removing useless code 2023-11-24 12:18:49 +01:00
aletempiac 43f4dccb4f run time improvements in computing the column multiplicity 2023-11-23 16:29:33 +01:00
Allen Ho a316847341 correct fanout count 2023-11-23 19:33:05 +08:00
aletempiac acdd08fd9b Performance improvements 2023-11-21 11:47:56 +01:00
aletempiac d10d450f38 Final implementation 2023-11-19 21:59:40 +01:00
aletempiac 219d6d86d6 Simplifying code 2023-11-19 19:33:19 +01:00
aletempiac 672fd1b629 removing not used methods 2023-11-19 18:53:54 +01:00
aletempiac f7a520b957 restructuring code 2023-11-19 18:51:50 +01:00
aletempiac 1d7dfd25c6 Improving ACD mapping 2023-11-17 16:58:17 +01:00
aletempiac 3d602e2f00 Adding sorting of columns in heuristic covering 2023-11-17 15:55:10 +01:00
aletempiac 1ca7a3a353 Remove symmetries in covering table 2023-11-17 15:49:29 +01:00
aletempiac b77bdeeb17 Enabling ACD for area 2023-11-16 19:21:29 +01:00
aletempiac 8aa57c5d54 Decisions on late arrival 2023-11-16 18:53:02 +01:00
aletempiac 548fd6afb2 New version of enumeration of combinations 2023-11-16 18:20:05 +01:00
aletempiac b32bbdfef3 Improving set covering using unitary cost 2023-11-16 15:33:19 +01:00
aletempiac dcc960beba Adding local search for covering 2023-11-15 21:57:29 +01:00
aletempiac c07080f818 Adding heuristic set covering solver 2023-11-15 21:32:34 +01:00
aletempiac 66cdd36d20 Runtime improvements in decomposition 2023-11-15 19:03:29 +01:00
aletempiac 1632dc0d4e First version of ACD 2023-11-15 18:38:00 +01:00
Alan Mishchenko 6ca7eab466 Prototype of integrating decomposition into "if". 2023-11-14 12:58:03 -08:00
Alan Mishchenko eb264c5d22 Suggested fixes. 2023-11-13 17:19:54 -08:00
WWFUG 67a2b97cf0 added -I options in &bmiter 2023-11-08 19:00:03 +08:00
Alan Mishchenko 04dba9eed9 Adding callback for wire caps during sizing. 2023-11-06 17:35:41 -08:00
Allen Ho 50010139ef why 2023-11-06 18:37:40 +08:00
Allen Ho ba64d6118b out-side box matching 2023-10-30 15:09:01 -07:00
Alan Mishchenko 5de12aa6b3 Experiments with SAT solving. 2023-10-23 11:30:44 -07:00
Alan Mishchenko 1bf21626c0 Bug fix. 2023-10-23 11:04:35 -07:00
Alan Mishchenko 76e8d21aaf Printout changes. 2023-10-23 10:48:43 -07:00
Alan Mishchenko 538ecb4515 Updating printouts. 2023-10-23 09:38:24 -07:00
Alan Mishchenko 01ad71b26f Experiments with verification. 2023-10-23 09:38:08 -07:00
Alan Mishchenko 8dbf8965fd Adding batch option to "scrgen". 2023-10-23 09:37:04 -07:00
Alan Mishchenko 652a0aaef7 Compiler warning. 2023-10-20 22:42:40 -07:00
Alan Mishchenko 72b423ba14 Experiments with SAT solving. 2023-10-20 20:53:43 -07:00
wjrforcyber c2fdb86a4d Refactor(Typo): Typo in ACD 2023-10-07 13:53:22 +08:00
wjrforcyber fb6a4722c2 Merge remote-tracking branch 'upstream/master' into typo 2023-10-07 13:50:29 +08:00
Alan Mishchenko 3c4c558656 Experiment with script generation. 2023-10-02 16:47:37 -07:00
Alan Mishchenko 65ccd3cc69 Enabled literal remapping. 2023-09-29 16:07:29 -07:00
Alan Mishchenko cc636a0d83 Experiments with verification. 2023-09-28 06:40:57 -07:00
wjrforcyber ecf6255985 Refactor(Typo):Missing a parameter fUseLutLib and use fSaveBest twice 2023-09-26 14:24:02 +08:00
Alan Mishchenko 0f11580fce Experiments with retiming. 2023-09-24 22:18:45 +08:00
wjrforcyber 3781c1df61 Refactor(Typo): Link is NOT FOUND page(not available), change to the book name 2023-09-24 19:31:37 +08:00
Alan Mishchenko 4d1618f600 Enable dumping Verilog with assign-statements. 2023-09-21 11:08:43 +08:00
Alan Mishchenko 73dac01c15 Warning regarding PathMatchSpec() on Windows. 2023-09-21 11:08:16 +08:00
Allen Ho 31ad17fa1a add abc9RecoverBoundary 2023-09-20 14:23:47 +08:00
Alan Mishchenko 7fd4b01fb3 Automatic script file generation. 2023-09-18 16:30:09 +08:00
Alan Mishchenko 09b0295c1a Adding aliases for some commands. 2023-09-18 16:27:54 +08:00
wjrforcyber eae19f7a62 Refactor(Typo): Typo in strash 2023-09-18 13:56:18 +08:00
wjrforcyber 05c897a753 Refactor(Typo): Typo in read_aiger 2023-09-17 19:34:56 +08:00
wjrforcyber e1db615384 Merge branch 'master' into typo 2023-09-17 13:28:57 +08:00
wjrforcyber 7ec8f17094 Refactor(Typo): Typo update in write_aiger message 2023-09-17 13:27:00 +08:00
Alan Mishchenko 9399faac48 Improvements to &gen_hie. 2023-09-17 12:40:33 +08:00
Alan Mishchenko 2f5b81119b Experiments with retiming. 2023-09-17 12:17:27 +08:00
wjrforcyber 6e1323caa2 Refactor(Typo): Typo update in bblif comment 2023-09-16 22:31:47 +08:00
wjrforcyber 136bae27d8 Refactor(Typo): Typo update in read_aiger comment 2023-09-16 19:43:03 +08:00
Alan Mishchenko 475c8dad8e Compiler problem. 2023-09-16 07:13:10 +08:00
Cunxi Yu 1261f71248
Merge branch 'berkeley-abc:master' into master 2023-09-15 13:25:27 -07:00
Alan Mishchenko 318d5cb54b Do not create spec outputs in the boundary miter. 2023-09-15 23:10:42 +08:00
Alan Mishchenko 57cc2bd089 Compiler problem. 2023-09-15 22:51:11 +08:00
Alan Mishchenko 09013f3a6e New command &gen_hie to generate hierarchical designs. 2023-09-15 22:44:31 +08:00
wjrforcyber 3a53a950aa Refactor(Typo): Typo update on buffer 2023-09-12 11:57:18 +08:00
wjrforcyber 7fe7449685 Refactor(Typo):Typo update on dnsize 2023-09-12 10:40:59 +08:00
Alan Mishchenko 1153b3b6b9 Commenting out an assert that signals a non-critical formance bug. 2023-09-11 12:12:52 +07:00
Alan Mishchenko 1ffdbbbebe Corner-case bug fix. 2023-09-11 10:46:38 +07:00
Alan Mishchenko 588122dc72 Writing an interface module when dumping Verilog. 2023-09-11 09:44:22 +07:00