mirror of https://github.com/YosysHQ/abc.git
Prototype of integrating decomposition into "if".
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@ -19447,7 +19447,7 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
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If_ManSetDefaultPars( pPars );
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pPars->pLutLib = (If_LibLut_t *)Abc_FrameReadLibLut();
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Extra_UtilGetoptReset();
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while ( ( c = Extra_UtilGetopt( argc, argv, "KCFAGRNTXYDEWSqaflepmrsdbgxyuojiktncvh" ) ) != EOF )
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while ( ( c = Extra_UtilGetopt( argc, argv, "KCFAGRNTXYDEWSqaflepmrsdbgxyzuojiktncvh" ) ) != EOF )
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{
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switch ( c )
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{
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@ -19652,6 +19652,9 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
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case 'y':
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pPars->fUserRecLib ^= 1;
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break;
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case 'z':
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pPars->fUserLutDec ^= 1;
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break;
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case 'u':
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pPars->fUserSesLib ^= 1;
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break;
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@ -19807,7 +19810,7 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
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pPars->pLutLib = NULL;
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}
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// modify for delay optimization
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if ( pPars->fDelayOpt || pPars->fDsdBalance || pPars->fDelayOptLut )
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if ( pPars->fDelayOpt || pPars->fDsdBalance || pPars->fDelayOptLut || pPars->fUserLutDec )
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{
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pPars->fTruth = 1;
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pPars->fCutMin = 1;
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@ -19953,7 +19956,7 @@ usage:
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sprintf(LutSize, "library" );
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else
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sprintf(LutSize, "%d", pPars->nLutSize );
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Abc_Print( -2, "usage: if [-KCFAGRNTXY num] [-DEW float] [-S str] [-qarlepmsdbgxyuojiktncvh]\n" );
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Abc_Print( -2, "usage: if [-KCFAGRNTXY num] [-DEW float] [-S str] [-qarlepmsdbgxyzuojiktncvh]\n" );
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Abc_Print( -2, "\t performs FPGA technology mapping of the network\n" );
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Abc_Print( -2, "\t-K num : the number of LUT inputs (2 < num < %d) [default = %s]\n", IF_MAX_LUTSIZE+1, LutSize );
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Abc_Print( -2, "\t-C num : the max number of priority cuts (0 < num < 2^12) [default = %d]\n", pPars->nCutsMax );
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@ -19982,6 +19985,7 @@ usage:
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Abc_Print( -2, "\t-g : toggles delay optimization by SOP balancing [default = %s]\n", pPars->fDelayOpt? "yes": "no" );
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Abc_Print( -2, "\t-x : toggles delay optimization by DSD balancing [default = %s]\n", pPars->fDsdBalance? "yes": "no" );
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Abc_Print( -2, "\t-y : toggles delay optimization with recorded library [default = %s]\n", pPars->fUserRecLib? "yes": "no" );
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Abc_Print( -2, "\t-z : toggles delay optimization with LUT decomposition [default = %s]\n", pPars->fUserLutDec? "yes": "no" );
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Abc_Print( -2, "\t-u : toggles delay optimization with SAT-based library [default = %s]\n", pPars->fUserSesLib? "yes": "no" );
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Abc_Print( -2, "\t-o : toggles using buffers to decouple combinational outputs [default = %s]\n", pPars->fUseBuffs? "yes": "no" );
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Abc_Print( -2, "\t-j : toggles enabling additional check [default = %s]\n", pPars->fEnableCheck07? "yes": "no" );
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@ -116,7 +116,7 @@ Abc_Ntk_t * Abc_NtkIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
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pPars->pTimesReq = Abc_NtkGetCoRequiredFloats(pNtk);
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// update timing info to reflect logic level
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if ( (pPars->fDelayOpt || pPars->fDsdBalance || pPars->fUserRecLib || pPars->fUserSesLib) && pNtk->pManTime )
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if ( (pPars->fDelayOpt || pPars->fDsdBalance || pPars->fUserRecLib || pPars->fUserSesLib || pPars->fUserLutDec) && pNtk->pManTime )
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{
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int c;
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if ( pNtk->AndGateDelay == 0.0 )
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@ -426,6 +426,30 @@ Hop_Obj_t * Abc_NodeBuildFromMini( Hop_Man_t * pMan, If_Man_t * p, If_Cut_t * pC
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return Abc_NodeBuildFromMiniInt( pMan, p->vArray, If_CutLeaveNum(pCut) );
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}
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/**Function*************************************************************
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Synopsis [Implements decomposed LUT-structure of the cut.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Hop_Obj_t * Abc_DecRecordToHop( Hop_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCutBest, If_Obj_t * pIfObj, Vec_Int_t * vCover )
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{
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// get the truth table
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// perform LUT-decomposition and return the LUT-structure
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// convert the LUT-structure into a set of logic nodes in Abc_Ntk_t
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// this is a placeholder, which takes the truth table and converts it into an AIG without LUT-decomposition
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extern Hop_Obj_t * Kit_TruthToHop( Hop_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory );
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word * pTruth = If_CutTruthW(pIfMan, pCutBest);
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assert( !pIfMan->pPars->fUseTtPerm );
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return Kit_TruthToHop( (Hop_Man_t *)pMan, (unsigned *)pTruth, If_CutLeaveNum(pCutBest), vCover );
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}
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/**Function*************************************************************
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Synopsis [Derive one node after FPGA mapping.]
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@ -464,7 +488,7 @@ Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t
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pNodeNew = Abc_NtkCreateNode( pNtkNew );
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// if ( pIfMan->pPars->pLutLib && pIfMan->pPars->pLutLib->fVarPinDelays )
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if ( !pIfMan->pPars->fDelayOpt && !pIfMan->pPars->fDelayOptLut && !pIfMan->pPars->fDsdBalance && !pIfMan->pPars->fUseTtPerm &&
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!pIfMan->pPars->pLutStruct && !pIfMan->pPars->fUserRecLib && !pIfMan->pPars->fUserSesLib && !pIfMan->pPars->nGateSize )
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!pIfMan->pPars->pLutStruct && !pIfMan->pPars->fUserRecLib && !pIfMan->pPars->fUserSesLib && !pIfMan->pPars->fUserLutDec && !pIfMan->pPars->nGateSize )
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If_CutRotatePins( pIfMan, pCutBest );
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if ( pIfMan->pPars->fUseCnfs || pIfMan->pPars->fUseMv )
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{
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@ -524,6 +548,11 @@ Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t
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extern Hop_Obj_t * Abc_RecToHop3( Hop_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCut, If_Obj_t * pIfObj );
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pNodeNew->pData = Abc_RecToHop3( (Hop_Man_t *)pNtkNew->pManFunc, pIfMan, pCutBest, pIfObj );
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}
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else if ( pIfMan->pPars->fUserLutDec )
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{
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extern Hop_Obj_t * Abc_DecRecordToHop( Hop_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCut, If_Obj_t * pIfObj, Vec_Int_t * vMemory );
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pNodeNew->pData = Abc_DecRecordToHop( (Hop_Man_t *)pNtkNew->pManFunc, pIfMan, pCutBest, pIfObj, vCover );
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}
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else
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{
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extern Hop_Obj_t * Kit_TruthToHop( Hop_Man_t * pMan, unsigned * pTruth, int nVars, Vec_Int_t * vMemory );
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@ -126,6 +126,7 @@ struct If_Par_t_
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int fDsdBalance; // special delay optimization
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int fUserRecLib; // use recorded library
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int fUserSesLib; // use SAT-based synthesis
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int fUserLutDec; // use LUT-based decomposition
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int fBidec; // use bi-decomposition
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int fUse34Spec; // use specialized matching
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int fUseBat; // use one specialized feature
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@ -765,7 +765,7 @@ void If_CutSort( If_Man_t * p, If_Set_t * pCutSet, If_Cut_t * pCut )
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if ( !pCut->fUseless &&
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(p->pPars->fUseDsd || p->pPars->pFuncCell2 || p->pPars->fUseBat ||
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p->pPars->pLutStruct || p->pPars->fUserRecLib || p->pPars->fUserSesLib ||
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p->pPars->pLutStruct || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fUserLutDec ||
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p->pPars->fEnableCheck07 || p->pPars->fUseCofVars || p->pPars->fUseAndVars || p->pPars->fUse34Spec ||
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p->pPars->fUseDsdTune || p->pPars->fEnableCheck75 || p->pPars->fEnableCheck75u || p->pPars->fUseCheck1 || p->pPars->fUseCheck2) )
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{
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@ -148,6 +148,32 @@ int * If_CutArrTimeProfile( If_Man_t * p, If_Cut_t * pCut )
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return p->pArrTimeProfile;
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}
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/**Function*************************************************************
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Synopsis [Returns the node's delay if its cut it LUT-decomposed.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int If_CutDelayLutDec( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj )
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{
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// get the truth table
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// get the cut leaves' arrival times
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// run LUT-decomposition in the evaluation mode
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// return expected arrival time at the output
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// this is a placeholder code, which is assume the cut has unit delay
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int i, ArrTimes = 0;
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for ( i = 0; i < If_CutLeaveNum(pCut); i++ )
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ArrTimes = Abc_MaxInt( ArrTimes, (int)If_ObjCutBest(If_CutLeaf(p, pCut, i))->Delay );
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return ArrTimes + 1;
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}
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/**Function*************************************************************
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Synopsis [Finds the best cut for the given node.]
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@ -166,7 +192,7 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
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If_Cut_t * pCut0R, * pCut1R;
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int fFunc0R, fFunc1R;
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int i, k, v, iCutDsd, fChange;
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int fSave0 = p->pPars->fDelayOpt || p->pPars->fDelayOptLut || p->pPars->fDsdBalance || p->pPars->fUserRecLib || p->pPars->fUserSesLib ||
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int fSave0 = p->pPars->fDelayOpt || p->pPars->fDelayOptLut || p->pPars->fDsdBalance || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fUserLutDec ||
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p->pPars->fUseDsdTune || p->pPars->fUseCofVars || p->pPars->fUseAndVars || p->pPars->fUse34Spec || p->pPars->pLutStruct || p->pPars->pFuncCell2 || p->pPars->fUseCheck1 || p->pPars->fUseCheck2;
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int fUseAndCut = (p->pPars->nAndDelay > 0) || (p->pPars->nAndArea > 0);
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assert( !If_ObjIsAnd(pObj->pFanin0) || pObj->pFanin0->pCutSet->nCuts > 0 );
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@ -208,6 +234,8 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
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pCut->fUseless = 1;
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}
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}
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else if ( p->pPars->fUserLutDec )
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pCut->Delay = If_CutDelayLutDec( p, pCut, pObj );
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else if ( p->pPars->fDelayOptLut )
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pCut->Delay = If_CutLutBalanceEval( p, pCut );
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else if( p->pPars->nGateSize > 0 )
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@ -436,6 +464,8 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
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pCut->fUseless = 1;
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}
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}
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else if ( p->pPars->fUserLutDec )
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pCut->Delay = If_CutDelayLutDec( p, pCut, pObj );
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else if ( p->pPars->fDelayOptLut )
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pCut->Delay = If_CutLutBalanceEval( p, pCut );
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else if( p->pPars->nGateSize > 0 )
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@ -507,7 +537,7 @@ void If_ObjPerformMappingChoice( If_Man_t * p, If_Obj_t * pObj, int Mode, int fP
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If_Set_t * pCutSet;
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If_Obj_t * pTemp;
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If_Cut_t * pCutTemp, * pCut;
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int i, fSave0 = p->pPars->fDelayOpt || p->pPars->fDelayOptLut || p->pPars->fDsdBalance || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fUse34Spec;
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int i, fSave0 = p->pPars->fDelayOpt || p->pPars->fDelayOptLut || p->pPars->fDsdBalance || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fUserLutDec || p->pPars->fUse34Spec;
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assert( pObj->pEquiv != NULL );
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// prepare
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