mirror of https://github.com/YosysHQ/abc.git
New command &gen_hie to generate hierarchical designs.
This commit is contained in:
Alan Mishchenko
parent
79456fadde
commit
09013f3a6e
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@ -1527,7 +1527,7 @@ extern void Gia_ManPrintStatsMiter( Gia_Man_t * p, int fVerbose )
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extern void Gia_ManSetRegNum( Gia_Man_t * p, int nRegs );
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extern void Gia_ManReportImprovement( Gia_Man_t * p, Gia_Man_t * pNew );
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extern void Gia_ManPrintNpnClasses( Gia_Man_t * p );
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extern void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int fVerBufs, int fInter );
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extern void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int fVerBufs, int fInter, int fInterComb );
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/*=== giaMem.c ===========================================================*/
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extern Gia_MmFixed_t * Gia_MmFixedStart( int nEntrySize, int nEntriesMax );
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extern void Gia_MmFixedStop( Gia_MmFixed_t * p, int fVerbose );
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@ -1291,7 +1291,7 @@ void Gia_ManDumpModuleName( FILE * pFile, char * pName )
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else
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fprintf( pFile, "_" );
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}
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void Gia_ManDumpInterface( Gia_Man_t * p, FILE * pFile )
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void Gia_ManDumpInterface2( Gia_Man_t * p, FILE * pFile )
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{
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int fPrintClk = 0;
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fprintf( pFile, "module " );
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@ -1324,7 +1324,6 @@ void Gia_ManDumpInterface( Gia_Man_t * p, FILE * pFile )
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fprintf( pFile, "endmodule\n\n" );
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}
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/**Function*************************************************************
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Synopsis [Compute arrival/required times.]
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@ -1407,7 +1406,7 @@ void Gia_ManWriteNames( FILE * pFile, char c, int n, Vec_Ptr_t * vNames, int Sta
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fFirst = 0;
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}
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}
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void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int fVerBufs, int fInter )
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void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int fVerBufs, int fInter, int fInterComb )
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{
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Gia_Obj_t * pObj;
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Vec_Bit_t * vInvs, * vUsed;
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@ -1415,6 +1414,13 @@ void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int
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int nDigitsI = Abc_Base10Log( Gia_ManPiNum(p) );
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int nDigitsO = Abc_Base10Log( Gia_ManPoNum(p) );
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int i, k, iObj, nRegs = Gia_ManRegNum(p);
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if ( fInterComb )
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{
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extern void Gia_ManDumpInterface( Gia_Man_t * p, char * pFileName );
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Gia_ManDumpInterface( p, pFileName );
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return;
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}
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FILE * pFile = fopen( pFileName, "wb" );
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if ( pFile == NULL )
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{
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@ -1423,7 +1429,7 @@ void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int
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}
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if ( fInter || nRegs )
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Gia_ManDumpInterface( p, pFile );
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Gia_ManDumpInterface2( p, pFile );
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//Gia_ManSetRegNum( p, 0 );
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p->nRegs = 0;
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@ -1588,6 +1594,201 @@ void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int
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Gia_ManSetRegNum( p, nRegs );
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Gia_ManDumpInterface( Gia_Man_t * p, char * pFileName )
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{
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Gia_Obj_t * pObj;
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Vec_Bit_t * vInvs, * vUsed;
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int nDigits = Abc_Base10Log( Gia_ManObjNum(p) );
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int nDigitsI = Abc_Base10Log( Gia_ManPiNum(p) );
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int nDigitsO = Abc_Base10Log( Gia_ManPoNum(p) );
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int i;
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FILE * pFile = fopen( pFileName, "wb" );
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if ( pFile == NULL )
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{
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printf( "Cannot open output file \"%s\".\n", pFileName );
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return;
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}
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vInvs = Gia_ManGenUsed( p, 0 );
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vUsed = Gia_ManGenUsed( p, 1 );
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fprintf( pFile, "module " );
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Gia_ManDumpModuleName( pFile, p->pName );
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fprintf( pFile, "_wrapper" );
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fprintf( pFile, " ( _i_, _o_ );\n\n" );
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fprintf( pFile, " input [%d:0] _i_;\n", Gia_ManCiNum(p)-1 );
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fprintf( pFile, " output [%d:0] _o_;\n\n", Gia_ManCoNum(p)-1 );
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fprintf( pFile, " wire " );
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Gia_ManWriteNames( pFile, 'x', Gia_ManPiNum(p), p->vNamesIn, 8, 4, NULL );
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fprintf( pFile, ";\n\n" );
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fprintf( pFile, " wire " );
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Gia_ManWriteNames( pFile, 'z', Gia_ManPoNum(p), p->vNamesOut, 9, 4, NULL );
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fprintf( pFile, ";\n\n" );
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fprintf( pFile, " assign { " );
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Gia_ManWriteNames( pFile, 'x', Gia_ManCiNum(p), p->vNamesIn, 8, 4, NULL );
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fprintf( pFile, " } = _i_;\n\n" );
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fprintf( pFile, " assign _o_ = { " );
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Gia_ManWriteNames( pFile, 'z', Gia_ManCoNum(p), p->vNamesOut, 9, 4, NULL );
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fprintf( pFile, " };\n\n" );
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if ( Vec_BitCount(vUsed) )
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{
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fprintf( pFile, " wire " );
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Gia_ManWriteNames( pFile, 'n', Gia_ManObjNum(p), NULL, 7, 4, vUsed );
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fprintf( pFile, ";\n\n" );
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}
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if ( Vec_BitCount(vInvs) )
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{
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fprintf( pFile, " wire " );
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Gia_ManWriteNames( pFile, 'i', Gia_ManObjNum(p), NULL, 7, 4, vInvs );
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fprintf( pFile, ";\n\n" );
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}
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// input inverters
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Gia_ManForEachCi( p, pObj, i )
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{
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if ( Vec_BitEntry(vUsed, Gia_ObjId(p, pObj)) )
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{
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fprintf( pFile, " buf ( %s,", Gia_ObjGetDumpName(NULL, 'n', Gia_ObjId(p, pObj), nDigits) );
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fprintf( pFile, " %s );\n", Gia_ObjGetDumpName(p->vNamesIn, 'x', i, nDigitsI) );
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}
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if ( Vec_BitEntry(vInvs, Gia_ObjId(p, pObj)) )
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{
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fprintf( pFile, " not ( %s,", Gia_ObjGetDumpName(NULL, 'i', Gia_ObjId(p, pObj), nDigits) );
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fprintf( pFile, " %s );\n", Gia_ObjGetDumpName(p->vNamesIn, 'x', i, nDigitsI) );
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}
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}
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// internal nodes and their inverters
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fprintf( pFile, "\n" );
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Gia_ManForEachAnd( p, pObj, i )
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{
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fprintf( pFile, " and ( %s,", Gia_ObjGetDumpName(NULL, 'n', i, nDigits) );
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fprintf( pFile, " %s,", Gia_ObjGetDumpName(NULL, (char)(Gia_ObjFaninC0(pObj)? 'i':'n'), Gia_ObjFaninId0(pObj, i), nDigits) );
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fprintf( pFile, " %s );\n", Gia_ObjGetDumpName(NULL, (char)(Gia_ObjFaninC1(pObj)? 'i':'n'), Gia_ObjFaninId1(pObj, i), nDigits) );
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if ( Vec_BitEntry(vInvs, i) )
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{
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fprintf( pFile, " not ( %s,", Gia_ObjGetDumpName(NULL, 'i', i, nDigits) );
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fprintf( pFile, " %s );\n", Gia_ObjGetDumpName(NULL, 'n', i, nDigits) );
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}
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}
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// output drivers
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fprintf( pFile, "\n" );
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Gia_ManForEachCo( p, pObj, i )
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{
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fprintf( pFile, " buf ( %s, ", Gia_ObjGetDumpName(p->vNamesOut, 'z', i, nDigitsO) );
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if ( Gia_ObjIsConst0(Gia_ObjFanin0(pObj)) )
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fprintf( pFile, "1\'b%d );\n", Gia_ObjFaninC0(pObj) );
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else
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fprintf( pFile, "%s );\n", Gia_ObjGetDumpName(NULL, (char)(Gia_ObjFaninC0(pObj)? 'i':'n'), Gia_ObjFaninId0p(p, pObj), nDigits) );
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}
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fprintf( pFile, "\nendmodule\n\n" );
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fclose( pFile );
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Vec_BitFree( vInvs );
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Vec_BitFree( vUsed );
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}
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/**Function*************************************************************
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Synopsis [Generate hierarchical design.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Gia_FreeMany( Gia_Man_t ** pGias, int nGias )
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{
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int i;
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for ( i = 0; i < nGias; i++ )
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Gia_ManStopP( &pGias[i] );
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}
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void Gia_GenSandwich( char ** pFNames, int nFNames )
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{
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FILE * pFile = NULL;
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char * pFileName = (char *)"sandwich.v";
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Gia_Man_t * pGias[16] = {0};
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int i, k;
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assert( nFNames <= 16 );
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for ( i = 0; i < nFNames; i++ )
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{
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FILE * pFile = fopen( pFNames[i], "rb" );
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if ( pFile == NULL ) {
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printf( "Cannot open input file \"%s\".\n", pFNames[i] );
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Gia_FreeMany( pGias, nFNames );
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return;
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}
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fclose( pFile );
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pGias[i] = Gia_AigerRead( pFNames[i], 0, 0, 0 );
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if ( pGias[i] == NULL ) {
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printf( "Failed to read an AIG from file \"%s\".\n", pFNames[i] );
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Gia_FreeMany( pGias, nFNames );
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return;
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}
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}
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for ( i = 0; i < nFNames-1; i++ )
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if ( Gia_ManPoNum(pGias[i]) < Gia_ManPiNum(pGias[i+1]) ) {
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printf( "AIG in file \"%s\" has fewer outputs than inputs of AIG in file \"%s\".\n", pFNames[i], pFNames[i+1] );
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Gia_FreeMany( pGias, nFNames );
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return;
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}
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pFile = fopen( pFileName, "wb" );
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if ( pFile == NULL )
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{
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printf( "Cannot open output file \"%s\".\n", pFileName );
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Gia_FreeMany( pGias, nFNames );
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return;
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}
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fprintf( pFile, "\n" );
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for ( i = 0; i < nFNames; i++ )
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fprintf( pFile, "`include \"%s\"\n", Extra_FileNameGenericAppend(pGias[i]->pSpec, ".v") );
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fprintf( pFile, "\n" );
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fprintf( pFile, "module sandwich ( in, out );\n" );
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fprintf( pFile, " input [%3d:0] in;\n", Gia_ManPiNum(pGias[0])-1 );
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fprintf( pFile, " output [%3d:0] out;\n", Gia_ManPoNum(pGias[nFNames-1])-1 );
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fprintf( pFile, " wire [%3d:0] tmp0 = in;\n", Gia_ManPiNum(pGias[0])-1 );
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for ( i = 0; i < nFNames; i++ ) {
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fprintf( pFile, " wire [%3d:0] tmp%d; ", Gia_ManPoNum(pGias[i])-1, i+1 );
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Gia_ManDumpModuleName( pFile, pGias[i]->pName );
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fprintf( pFile, "_wrapper" );
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for ( k = strlen(pGias[i]->pName); k < 24; k++ )
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fprintf( pFile, " " );
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fprintf( pFile, " i%d ( tmp%d, tmp%d );\n", i+1, i, i+1 );
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}
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fprintf( pFile, " assign out = tmp%d;\n", nFNames );
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fprintf( pFile, "endmodule\n" );
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fclose( pFile );
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for ( i = 0; i < nFNames; i++ ) {
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Gia_ManDumpVerilog( pGias[i], Extra_FileNameGenericAppend(pGias[i]->pSpec, ".v"), NULL, 0, 0, 1 );
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printf( "Dumped Verilog file \"%s\"\n", Extra_FileNameGenericAppend(pGias[i]->pSpec, ".v") );
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}
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Gia_FreeMany( pGias, nFNames );
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printf( "Dumped hierarchical design into file \"%s\"\n", pFileName );
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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@ -595,6 +595,7 @@ static int Abc_CommandAbc9Cfs ( Abc_Frame_t * pAbc, int argc, cha
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static int Abc_CommandAbc9ProdAdd ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandAbc9AddFlop ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandAbc9BMiter ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandAbc9GenHie ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandAbc9Test ( Abc_Frame_t * pAbc, int argc, char ** argv );
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@ -1364,6 +1365,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
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Cmd_CommandAdd( pAbc, "ABC9", "&prodadd", Abc_CommandAbc9ProdAdd, 0 );
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Cmd_CommandAdd( pAbc, "ABC9", "&addflop", Abc_CommandAbc9AddFlop, 0 );
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Cmd_CommandAdd( pAbc, "ABC9", "&bmiter", Abc_CommandAbc9BMiter, 0 );
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Cmd_CommandAdd( pAbc, "ABC9", "&gen_hie", Abc_CommandAbc9GenHie, 0 );
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Cmd_CommandAdd( pAbc, "ABC9", "&test", Abc_CommandAbc9Test, 0 );
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{
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@ -31762,13 +31764,14 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv )
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int fUnique = 0;
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int fVerilog = 0;
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int fInter = 0;
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int fInterComb = 0;
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int fVerBufs = 0;
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int fMiniAig = 0;
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int fMiniLut = 0;
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int fWriteNewLine = 0;
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int fVerbose = 0;
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Extra_UtilGetoptReset();
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while ( ( c = Extra_UtilGetopt( argc, argv, "upibmlnvh" ) ) != EOF )
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while ( ( c = Extra_UtilGetopt( argc, argv, "upicbmlnvh" ) ) != EOF )
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{
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switch ( c )
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{
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@ -31781,6 +31784,9 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv )
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case 'i':
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fInter ^= 1;
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break;
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case 'c':
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fInterComb ^= 1;
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break;
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case 'b':
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fVerBufs ^= 1;
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break;
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@ -31822,7 +31828,7 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv )
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Gia_ManStop( pGia );
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}
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else if ( fVerilog )
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Gia_ManDumpVerilog( pAbc->pGia, pFileName, NULL, fVerBufs, fInter );
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Gia_ManDumpVerilog( pAbc->pGia, pFileName, NULL, fVerBufs, fInter, fInterComb );
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else if ( fMiniAig )
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Gia_ManWriteMiniAig( pAbc->pGia, pFileName );
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else if ( fMiniLut )
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@ -31832,11 +31838,12 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv )
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return 0;
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usage:
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Abc_Print( -2, "usage: &w [-upibmlnvh] <file>\n" );
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Abc_Print( -2, "usage: &w [-upicbmlnvh] <file>\n" );
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Abc_Print( -2, "\t writes the current AIG into the AIGER file\n" );
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Abc_Print( -2, "\t-u : toggle writing canonical AIG structure [default = %s]\n", fUnique? "yes" : "no" );
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Abc_Print( -2, "\t-p : toggle writing Verilog with 'and' and 'not' [default = %s]\n", fVerilog? "yes" : "no" );
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Abc_Print( -2, "\t-i : toggle writing the interface module in Verilog [default = %s]\n", fInter? "yes" : "no" );
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Abc_Print( -2, "\t-c : toggle writing the interface module in Verilog [default = %s]\n", fInterComb? "yes" : "no" );
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Abc_Print( -2, "\t-b : toggle writing additional buffers in Verilog [default = %s]\n", fVerBufs? "yes" : "no" );
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Abc_Print( -2, "\t-m : toggle writing MiniAIG rather than AIGER [default = %s]\n", fMiniAig? "yes" : "no" );
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Abc_Print( -2, "\t-l : toggle writing MiniLUT rather than AIGER [default = %s]\n", fMiniLut? "yes" : "no" );
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@ -51569,6 +51576,50 @@ usage:
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return 1;
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Abc_CommandAbc9GenHie( Abc_Frame_t * pAbc, int argc, char ** argv )
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{
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extern void Gia_GenSandwich( char ** pFNames, int nFNames );
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int c, fVerbose = 0;
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Extra_UtilGetoptReset();
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while ( ( c = Extra_UtilGetopt( argc, argv, "vh" ) ) != EOF )
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{
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switch ( c )
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{
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case 'v':
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fVerbose ^= 1;
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break;
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case 'h':
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goto usage;
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default:
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goto usage;
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}
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}
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char ** pArgvNew = argv + globalUtilOptind;
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int nArgcNew = argc - globalUtilOptind;
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Gia_GenSandwich( pArgvNew, nArgcNew );
|
||||
return 0;
|
||||
usage:
|
||||
Abc_Print( -2, "usage: &gen_hie [-vh] <file[1]> <file[2]> ... <file[N]>\n" );
|
||||
Abc_Print( -2, "\t generates a hierarchical design\n" );
|
||||
Abc_Print( -2, "\t-v : toggles printing verbose information [default = %s]\n", fVerbose? "yes": "no" );
|
||||
Abc_Print( -2, "\t-h : print the command usage\n");
|
||||
Abc_Print( -2, "\t<files> : the AIG files for the instance modules\n");
|
||||
Abc_Print( -2, "\t (the PO count of <file[i]> should not be less than the PI count of <file[i+1]>)\n");
|
||||
return 1;}
|
||||
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
|
|
|||
Loading…
Reference in New Issue