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Formatting, renaming, and cleaning code

This commit is contained in:
aletempiac 2023-11-27 13:38:36 +01:00
parent 6097fd4349
commit b3d2419d9a
11 changed files with 131 additions and 99 deletions
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49
src/acd/ac_decomposition.hpp
View File

@ -1,28 +1,20 @@
/* mockturtle: C++ logic network library
* Copyright (C) 2018-2023 EPFL
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/**C++File**************************************************************
FileName [ac_decomposition.hpp]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Ashenhurst-Curtis decomposition.]
Synopsis [Interface with the FPGA mapping package.]
Author [Alessandro Tempia Calvino]
Affiliation [EPFL]
Date [Ver. 1.0. Started - November 20, 2023.]
***********************************************************************/
/*!
\file ac_decomposition.hpp
\brief Ashenhurst-Curtis decomposition
@ -39,7 +31,6 @@
#include <cstdint>
#include <type_traits>
#include <unordered_map>
#include <unordered_set>
#include <vector>
#include "kitty_constants.hpp"
@ -49,7 +40,7 @@
#include "kitty_operators.hpp"
#include "kitty_static_tt.hpp"
namespace mockturtle
namespace acd
{
/*! \brief Parameters for ac_decomposition */
@ -346,10 +337,10 @@ private:
{
for ( auto j = 0; j < ( 64 >> free_set_size ); ++j )
{
uint32_t fs_fn = static_cast<uint32_t>( *it & masks[free_set_size] );
uint64_t fs_fn = *it & masks[free_set_size];
if ( fs_fn != prev )
{
multiplicity_set[size++] = fs_fn;
multiplicity_set[size++] = static_cast<uint32_t>( fs_fn );
prev = fs_fn;
}
*it >>= ( 1u << free_set_size );
@ -1303,6 +1294,6 @@ private:
std::array<uint32_t, max_num_vars> permutations;
};
} // namespace mockturtle
} // namespace acd
#endif // _ACD_H_

22
src/acd/ac_wrapper.cpp
View File

@ -1,9 +1,27 @@
/**C++File**************************************************************
FileName [ac_wrapper.cpp]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Ashenhurst-Curtis decomposition.]
Synopsis [Interface with the FPGA mapping package.]
Author [Alessandro Tempia Calvino]
Affiliation [EPFL]
Date [Ver. 1.0. Started - November 20, 2023.]
***********************************************************************/
#include "ac_wrapper.h"
#include "ac_decomposition.hpp"
int acd_evaluate( word * pTruth, unsigned nVars, int lutSize, unsigned *pdelay, unsigned *cost, int try_no_late_arrival )
{
using namespace mockturtle;
using namespace acd;
ac_decomposition_params ps;
ps.lut_size = lutSize;
@ -27,7 +45,7 @@ int acd_evaluate( word * pTruth, unsigned nVars, int lutSize, unsigned *pdelay,
int acd_decompose( word * pTruth, unsigned nVars, int lutSize, unsigned *pdelay, unsigned char *decomposition )
{
using namespace mockturtle;
using namespace acd;
ac_decomposition_params ps;
ps.lut_size = lutSize;

18
src/acd/ac_wrapper.h
View File

@ -1,3 +1,21 @@
/**C++File**************************************************************
FileName [ac_wrapper.h]
SystemName [ABC: Logic synthesis and verification system.]
PackageName [Ashenhurst-Curtis decomposition.]
Synopsis [Interface with the FPGA mapping package.]
Author [Alessandro Tempia Calvino]
Affiliation [EPFL]
Date [Ver. 1.0. Started - November 20, 2023.]
***********************************************************************/
#pragma once
#ifndef __ACD_WRAPPER_H_
#define __ACD_WRAPPER_H_

45
src/base/abci/abc.c
View File

@ -19447,7 +19447,7 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
If_ManSetDefaultPars( pPars );
pPars->pLutLib = (If_LibLut_t *)Abc_FrameReadLibLut();
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "KCFAGRNTXYDEWSqaflepmrsdbgxyuojiktnczvh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "KCFAGRNTXYZDEWSqaflepmrsdbgxyzuojiktncvh" ) ) != EOF )
{
switch ( c )
{
@ -19563,6 +19563,17 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
if ( pPars->nAndDelay < 0 )
goto usage;
break;
case 'Z':
if ( globalUtilOptind >= argc )
{
Abc_Print( -1, "Command line switch \"-Z\" should be followed by a positive integer 3, 4, 5, or 6.\n" );
goto usage;
}
pPars->nLutDecSize = atoi(argv[globalUtilOptind]);
globalUtilOptind++;
if ( pPars->nLutDecSize < 3 || pPars->nLutDecSize > 6 )
goto usage;
break;
case 'D':
if ( globalUtilOptind >= argc )
{
@ -19652,6 +19663,9 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'y':
pPars->fUserRecLib ^= 1;
break;
case 'z':
pPars->fUserLutDec ^= 1;
break;
case 'u':
pPars->fUserSesLib ^= 1;
break;
@ -19676,9 +19690,6 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'c':
pPars->fUseTtPerm ^= 1;
break;
case 'z':
pPars->fAcd ^= 1;
break;
case 'v':
pPars->fVerbose ^= 1;
break;
@ -19794,6 +19805,25 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
pPars->fCutMin = 1;
}
if ( pPars->fUserLutDec )
{
if ( pPars->nLutDecSize == 0 )
{
Abc_Print( -1, "LUT decomposition size (%d) must be set.\n", pPars->nLutDecSize );
return 1;
}
if ( pPars->nLutDecSize >= pPars->nLutSize )
{
Abc_Print( -1, "LUT size (%d) must be greater than the LUT decomposition size (%d).\n", pPars->nLutSize, pPars->nLutDecSize );
return 1;
}
if ( pPars->nLutSize < 4 || pPars->nLutSize > 10 )
{
Abc_Print( -1, "This feature only works for [4;10]-LUTs.\n" );
return 1;
}
}
// enable truth table computation if cut minimization is selected
if ( pPars->fCutMin )
{
@ -19810,7 +19840,7 @@ int Abc_CommandIf( Abc_Frame_t * pAbc, int argc, char ** argv )
pPars->pLutLib = NULL;
}
// modify for delay optimization
if ( pPars->fDelayOpt || pPars->fDsdBalance || pPars->fDelayOptLut || pPars->fAcd )
if ( pPars->fDelayOpt || pPars->fDsdBalance || pPars->fDelayOptLut || pPars->fUserLutDec )
{
pPars->fTruth = 1;
pPars->fCutMin = 1;
@ -19956,7 +19986,7 @@ usage:
sprintf(LutSize, "library" );
else
sprintf(LutSize, "%d", pPars->nLutSize );
Abc_Print( -2, "usage: if [-KCFAGRNTXY num] [-DEW float] [-S str] [-qarlepmsdbgxyuojiktncvh]\n" );
Abc_Print( -2, "usage: if [-KCFAGRNTXYZ num] [-DEW float] [-S str] [-qarlepmsdbgxyzuojiktncvh]\n" );
Abc_Print( -2, "\t performs FPGA technology mapping of the network\n" );
Abc_Print( -2, "\t-K num : the number of LUT inputs (2 < num < %d) [default = %s]\n", IF_MAX_LUTSIZE+1, LutSize );
Abc_Print( -2, "\t-C num : the max number of priority cuts (0 < num < 2^12) [default = %d]\n", pPars->nCutsMax );
@ -19968,6 +19998,7 @@ usage:
Abc_Print( -2, "\t-T num : the type of LUT structures [default = any]\n" );
Abc_Print( -2, "\t-X num : delay of AND-gate in LUT library units [default = %d]\n", pPars->nAndDelay );
Abc_Print( -2, "\t-Y num : area of AND-gate in LUT library units [default = %d]\n", pPars->nAndArea );
Abc_Print( -2, "\t-Z num : the number of LUT inputs for LUT decomposition [default = %d]\n", pPars->nLutDecSize );
Abc_Print( -2, "\t-D float : sets the delay constraint for the mapping [default = %s]\n", Buffer );
Abc_Print( -2, "\t-E float : sets epsilon used for tie-breaking [default = %f]\n", pPars->Epsilon );
Abc_Print( -2, "\t-W float : sets wire delay between adjects LUTs [default = %f]\n", pPars->WireDelay );
@ -19985,6 +20016,7 @@ usage:
Abc_Print( -2, "\t-g : toggles delay optimization by SOP balancing [default = %s]\n", pPars->fDelayOpt? "yes": "no" );
Abc_Print( -2, "\t-x : toggles delay optimization by DSD balancing [default = %s]\n", pPars->fDsdBalance? "yes": "no" );
Abc_Print( -2, "\t-y : toggles delay optimization with recorded library [default = %s]\n", pPars->fUserRecLib? "yes": "no" );
Abc_Print( -2, "\t-z : toggles delay optimization with LUT decomposition [default = %s]\n", pPars->fUserLutDec? "yes": "no" );
Abc_Print( -2, "\t-u : toggles delay optimization with SAT-based library [default = %s]\n", pPars->fUserSesLib? "yes": "no" );
Abc_Print( -2, "\t-o : toggles using buffers to decouple combinational outputs [default = %s]\n", pPars->fUseBuffs? "yes": "no" );
Abc_Print( -2, "\t-j : toggles enabling additional check [default = %s]\n", pPars->fEnableCheck07? "yes": "no" );
@ -19993,7 +20025,6 @@ usage:
Abc_Print( -2, "\t-t : toggles optimizing average rather than maximum level [default = %s]\n", pPars->fDoAverage? "yes": "no" );
Abc_Print( -2, "\t-n : toggles computing DSDs of the cut functions [default = %s]\n", pPars->fUseDsd? "yes": "no" );
Abc_Print( -2, "\t-c : toggles computing truth tables in a new way [default = %s]\n", pPars->fUseTtPerm? "yes": "no" );
Abc_Print( -2, "\t-z : toggles using ACD decomposition [default = %s]\n", pPars->fAcd? "yes": "no" );
Abc_Print( -2, "\t-v : toggles verbose output [default = %s]\n", pPars->fVerbose? "yes": "no" );
Abc_Print( -2, "\t-h : prints the command usage\n");
return 1;

16
src/base/abci/abcIf.c
View File

@ -116,7 +116,7 @@ Abc_Ntk_t * Abc_NtkIf( Abc_Ntk_t * pNtk, If_Par_t * pPars )
pPars->pTimesReq = Abc_NtkGetCoRequiredFloats(pNtk);
// update timing info to reflect logic level
if ( (pPars->fDelayOpt || pPars->fDsdBalance || pPars->fUserRecLib || pPars->fUserSesLib || pPars->fAcd) && pNtk->pManTime )
if ( (pPars->fDelayOpt || pPars->fDsdBalance || pPars->fUserRecLib || pPars->fUserSesLib || pPars->fUserLutDec) && pNtk->pManTime )
{
int c;
if ( pNtk->AndGateDelay == 0.0 )
@ -443,7 +443,7 @@ Hop_Obj_t * Abc_NodeBuildFromMini( Hop_Man_t * pMan, If_Man_t * p, If_Cut_t * pC
int v;
If_Obj_t * pIfLeaf;
if ( pCutBest->nLeaves <= 6 )
if ( pCutBest->nLeaves <= pIfMan->pPars->nLutDecSize )
{
/* add fanins */
If_CutForEachLeaf( pIfMan, pCutBest, pIfLeaf, v )
@ -456,11 +456,11 @@ Hop_Obj_t * Abc_NodeBuildFromMini( Hop_Man_t * pMan, If_Man_t * p, If_Cut_t * pC
}
// get the delay profile
unsigned delayProfile = pCutBest->acdDelay;
unsigned delayProfile = pCutBest->decDelay;
// perform LUT-decomposition and return the LUT-structure
unsigned char decompArray[92];
int val = acd_decompose( pTruth, pCutBest->nLeaves, 6, &(delayProfile), decompArray );
int val = acd_decompose( pTruth, pCutBest->nLeaves, pIfMan->pPars->nLutDecSize, &(delayProfile), decompArray );
assert( val == 0 );
// convert the LUT-structure into a set of logic nodes in Abc_Ntk_t
@ -474,7 +474,7 @@ Hop_Obj_t * Abc_NodeBuildFromMini( Hop_Man_t * pMan, If_Man_t * p, If_Cut_t * pC
Abc_Obj_t *pNewNodes[5];
/* create intermediate LUTs*/
assert( decompArray[1] - 1 <= 5 );
assert( decompArray[1] <= 6 );
Abc_Obj_t * pFanin;
for ( i = 0; i < decompArray[1]; ++i )
{
@ -577,14 +577,14 @@ Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t
pNodeNew = Abc_NtkCreateNode( pNtkNew );
// if ( pIfMan->pPars->pLutLib && pIfMan->pPars->pLutLib->fVarPinDelays )
if ( !pIfMan->pPars->fDelayOpt && !pIfMan->pPars->fDelayOptLut && !pIfMan->pPars->fDsdBalance && !pIfMan->pPars->fUseTtPerm &&
!pIfMan->pPars->pLutStruct && !pIfMan->pPars->fAcd && !pIfMan->pPars->fUserRecLib && !pIfMan->pPars->fUserSesLib && !pIfMan->pPars->nGateSize )
!pIfMan->pPars->pLutStruct && !pIfMan->pPars->fUserLutDec && !pIfMan->pPars->fUserRecLib && !pIfMan->pPars->fUserSesLib && !pIfMan->pPars->nGateSize )
If_CutRotatePins( pIfMan, pCutBest );
if ( pIfMan->pPars->fUseCnfs || pIfMan->pPars->fUseMv )
{
If_CutForEachLeafReverse( pIfMan, pCutBest, pIfLeaf, i )
Abc_ObjAddFanin( pNodeNew, Abc_NodeFromIf_rec(pNtkNew, pIfMan, pIfLeaf, vCover) );
}
else if ( pIfMan->pPars->fAcd )
else if ( pIfMan->pPars->fUserLutDec )
{
If_CutForEachLeaf( pIfMan, pCutBest, pIfLeaf, i )
Abc_NodeFromIf_rec(pNtkNew, pIfMan, pIfLeaf, vCover);
@ -642,7 +642,7 @@ Abc_Obj_t * Abc_NodeFromIf_rec( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Obj_t
extern Hop_Obj_t * Abc_RecToHop3( Hop_Man_t * pMan, If_Man_t * pIfMan, If_Cut_t * pCut, If_Obj_t * pIfObj );
pNodeNew->pData = Abc_RecToHop3( (Hop_Man_t *)pNtkNew->pManFunc, pIfMan, pCutBest, pIfObj );
}
else if ( pIfMan->pPars->fAcd )
else if ( pIfMan->pPars->fUserLutDec )
{
extern void Abc_DecRecordToHop( Abc_Ntk_t * pNtkNew, If_Man_t * pIfMan, If_Cut_t * pCut, If_Obj_t * pIfObj, Vec_Int_t * vMemory, Abc_Obj_t * pNodeTop );
Abc_DecRecordToHop( pNtkNew, pIfMan, pCutBest, pIfObj, vCover, pNodeNew );

12
src/map/if/if.h
View File

@ -113,6 +113,7 @@ struct If_Par_t_
int nStructType; // type of the structure
int nAndDelay; // delay of AND-gate in LUT library units
int nAndArea; // area of AND-gate in LUT library units
int nLutDecSize; // the LUT size for decomposition
int fPreprocess; // preprossing
int fArea; // area-oriented mapping
int fFancy; // a fancy feature
@ -146,7 +147,7 @@ struct If_Par_t_
int fDeriveLuts; // enables deriving LUT structures
int fDoAverage; // optimize average rather than maximum level
int fHashMapping; // perform AIG hashing after mapping
int fAcd; // perform AIG hashing after mapping
int fUserLutDec; // perform AIG hashing after mapping
int fVerbose; // the verbosity flag
int fVerboseTrace; // the verbosity flag
char * pLutStruct; // LUT structure
@ -281,7 +282,6 @@ struct If_Man_t_
int pDumpIns[16];
Vec_Str_t * vMarks;
Vec_Int_t * vVisited2;
int useLimitAdc;
// timing manager
Tim_Man_t * pManTim;
@ -305,7 +305,6 @@ struct If_Cut_t_
int iCutFunc; // TT ID of the cut
int uMaskFunc; // polarity bitmask
unsigned uSign; // cut signature
unsigned acdDelay; // Computed pin delay during ACD
unsigned Cost : 12; // the user's cost of the cut (related to IF_COST_MAX)
unsigned fCompl : 1; // the complemented attribute
unsigned fUser : 1; // using the user's area and delay
@ -313,6 +312,7 @@ struct If_Cut_t_
unsigned fAndCut : 1; // matched with AND gate
unsigned nLimit : 8; // the maximum number of leaves
unsigned nLeaves : 8; // the number of leaves
unsigned decDelay: 16; // pin-to-pin decomposition delay
int pLeaves[0];
};
@ -570,9 +570,9 @@ extern int If_CutSopBalancePinDelaysInt( Vec_Int_t * vCover, int * p
extern int If_CutSopBalancePinDelays( If_Man_t * p, If_Cut_t * pCut, char * pPerm );
extern int If_CutLutBalanceEval( If_Man_t * p, If_Cut_t * pCut );
extern int If_CutLutBalancePinDelays( If_Man_t * p, If_Cut_t * pCut, char * pPerm );
extern int If_AcdEval( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj, int optDelay, int fFirst );
extern int If_AcdReEval( If_Man_t * p, If_Cut_t * pCut );
extern float If_AcdLeafProp( If_Man_t * p, If_Cut_t * pCut, int i, float required );
extern int If_LutDecEval( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj, int optDelay, int fFirst );
extern int If_LutDecReEval( If_Man_t * p, If_Cut_t * pCut );
extern float If_LutDecPinRequired( If_Man_t * p, If_Cut_t * pCut, int i, float required );
/*=== ifDsd.c =============================================================*/
extern If_DsdMan_t * If_DsdManAlloc( int nVars, int nLutSize );
extern void If_DsdManAllocIsops( If_DsdMan_t * p, int nLutSize );

28
src/map/if/ifCore.c
View File

@ -62,7 +62,7 @@ void If_ManSetDefaultPars( If_Par_t * pPars )
pPars->fPower = 0;
pPars->fCutMin = 0;
pPars->fBidec = 0;
pPars->fAcd = 0;
pPars->fUserLutDec = 0;
pPars->fVerbose = 0;
}
@ -107,16 +107,10 @@ int If_ManPerformMappingComb( If_Man_t * p )
If_Obj_t * pObj;
abctime clkTotal = Abc_Clock();
int i;
p->useLimitAdc = 1;
//p->vVisited2 = Vec_IntAlloc( 100 );
//p->vMarks = Vec_StrStart( If_ManObjNum(p) );
// if ( p->pPars->fAcd )
// {
// p->pPars->nLutSize = 6;
// }
// set arrival times and fanout estimates
If_ManForEachCi( p, pObj, i )
{
@ -128,11 +122,7 @@ int If_ManPerformMappingComb( If_Man_t * p )
if ( p->pPars->fPreprocess && !p->pPars->fArea )
{
// map for delay
if ( p->pPars->fAcd )
p->useLimitAdc = 0;
If_ManPerformMappingRound( p, p->pPars->nCutsMax, 0, 1, 1, "Delay" );
if ( p->pPars->fAcd )
p->useLimitAdc = 1;
// map for delay second option
p->pPars->fFancy = 1;
@ -155,33 +145,17 @@ int If_ManPerformMappingComb( If_Man_t * p )
// area flow oriented mapping
for ( i = 0; i < p->pPars->nFlowIters; i++ )
{
// if ( p->pPars->fAcd && i == 0 )
// {
// p->useLimitAdc = 0;
// }
If_ManPerformMappingRound( p, p->pPars->nCutsMax, 1, 0, 0, "Flow" );
if ( p->pPars->fExpRed )
If_ManImproveMapping( p );
// if ( p->pPars->fAcd && i == 0 )
// {
// p->useLimitAdc = 1;
// }
}
// area oriented mapping
for ( i = 0; i < p->pPars->nAreaIters; i++ )
{
// if ( p->pPars->fAcd && i == 0 )
// {
// p->useLimitAdc = 0;
// }
If_ManPerformMappingRound( p, p->pPars->nCutsMax, 2, 0, 0, "Area" );
if ( p->pPars->fExpRed )
If_ManImproveMapping( p );
// if ( p->pPars->fAcd && i == 0 )
// {
// p->useLimitAdc = 1;
// }
}
if ( p->pPars->fVerbose )

2
src/map/if/ifCut.c
View File

@ -761,7 +761,7 @@ void If_CutSort( If_Man_t * p, If_Set_t * pCutSet, If_Cut_t * pCut )
if ( !pCut->fUseless &&
(p->pPars->fUseDsd || p->pPars->pFuncCell2 || p->pPars->fUseBat ||
p->pPars->pLutStruct || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fAcd ||
p->pPars->pLutStruct || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fUserLutDec ||
p->pPars->fEnableCheck07 || p->pPars->fUseCofVars || p->pPars->fUseAndVars || p->pPars->fUse34Spec ||
p->pPars->fUseDsdTune || p->pPars->fEnableCheck75 || p->pPars->fEnableCheck75u || p->pPars->fUseCheck1 || p->pPars->fUseCheck2) )
{

20
src/map/if/ifDelay.c
View File

@ -412,11 +412,11 @@ int If_CutLutBalanceEval( If_Man_t * p, If_Cut_t * pCut )
}
}
int If_AcdEval( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj, int optDelay, int fFirst )
int If_LutDecEval( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj, int optDelay, int fFirst )
{
pCut->fUser = 1;
pCut->Cost = pCut->nLeaves > 1 ? 1 : 0;
pCut->acdDelay = 0;
pCut->decDelay = 0;
if ( pCut->nLeaves == 0 ) // const
{
assert( Abc_Lit2Var(If_CutTruthLit(pCut)) == 0 );
@ -428,7 +428,7 @@ int If_AcdEval( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj, int optDelay, in
return (int)If_ObjCutBest(If_CutLeaf(p, pCut, 0))->Delay;
}
int LutSize = 6;
int LutSize = p->pPars->nLutDecSize;
int i, leaf_delay;
int DelayMax = -1, nLeafMax = 0;
unsigned uLeafMask = 0;
@ -450,7 +450,7 @@ int If_AcdEval( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj, int optDelay, in
}
if ( If_CutLeaveNum(pCut) <= LutSize )
{
pCut->acdDelay = ( 1 << LutSize ) - 1;
pCut->decDelay = ( 1 << LutSize ) - 1;
return DelayMax + 1;
}
@ -473,7 +473,7 @@ int If_AcdEval( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj, int optDelay, in
}
/* Too many late-arriving signals */
if ( nLeafMax > LutSize / 2 )
if ( nLeafMax == LutSize )
{
if ( use_late_arrival )
{
@ -493,7 +493,7 @@ int If_AcdEval( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj, int optDelay, in
int val = acd_evaluate( pTruth, pCut->nLeaves, LutSize, &uLeafMask, &cost, !use_late_arrival );
/* not feasible decomposition */
pCut->acdDelay = uLeafMask;
pCut->decDelay = uLeafMask;
if ( val < 0 )
{
pCut->Cost = IF_COST_MAX;
@ -505,7 +505,7 @@ int If_AcdEval( If_Man_t * p, If_Cut_t * pCut, If_Obj_t * pObj, int optDelay, in
return DelayMax + val;
}
int If_AcdReEval( If_Man_t * p, If_Cut_t * pCut )
int If_LutDecReEval( If_Man_t * p, If_Cut_t * pCut )
{
// pCut->fUser = 1;
@ -526,14 +526,14 @@ int If_AcdReEval( If_Man_t * p, If_Cut_t * pCut )
for ( i = 0; i < If_CutLeaveNum(pCut); i++ )
{
leaf_delay = If_ObjCutBest(If_CutLeaf(p, pCut, i))->Delay;
leaf_delay += ( ( pCut->acdDelay >> i ) & 1 ) == 0 ? 2 : 1;
leaf_delay += ( ( pCut->decDelay >> i ) & 1 ) == 0 ? 2 : 1;
DelayMax = Abc_MaxInt( leaf_delay, DelayMax );
}
return DelayMax;
}
float If_AcdLeafProp( If_Man_t * p, If_Cut_t * pCut, int i, float required )
float If_LutDecPinRequired( If_Man_t * p, If_Cut_t * pCut, int i, float required )
{
if ( pCut->nLeaves == 0 ) // const
{
@ -546,7 +546,7 @@ float If_AcdLeafProp( If_Man_t * p, If_Cut_t * pCut, int i, float required )
return 0;
}
return ( ( pCut->acdDelay >> i ) & 1 ) == 0 ? 2 : 1;
return ( ( pCut->decDelay >> i ) & 1 ) == 0 ? 2 : 1;
}
/*

14
src/map/if/ifMap.c
View File

@ -166,7 +166,7 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
If_Cut_t * pCut0R, * pCut1R;
int fFunc0R, fFunc1R;
int i, k, v, iCutDsd, fChange;
int fSave0 = p->pPars->fDelayOpt || p->pPars->fDelayOptLut || p->pPars->fDsdBalance || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fAcd ||
int fSave0 = p->pPars->fDelayOpt || p->pPars->fDelayOptLut || p->pPars->fDsdBalance || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fUserLutDec ||
p->pPars->fUseDsdTune || p->pPars->fUseCofVars || p->pPars->fUseAndVars || p->pPars->fUse34Spec || p->pPars->pLutStruct || p->pPars->pFuncCell2 || p->pPars->fUseCheck1 || p->pPars->fUseCheck2;
int fUseAndCut = (p->pPars->nAndDelay > 0) || (p->pPars->nAndArea > 0);
assert( !If_ObjIsAnd(pObj->pFanin0) || pObj->pFanin0->pCutSet->nCuts > 0 );
@ -208,9 +208,9 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
pCut->fUseless = 1;
}
}
else if ( p->pPars->fAcd )
else if ( p->pPars->fUserLutDec )
{
pCut->Delay = If_AcdReEval( p, pCut );
pCut->Delay = If_LutDecReEval( p, pCut );
}
else if ( p->pPars->fDelayOptLut )
pCut->Delay = If_CutLutBalanceEval( p, pCut );
@ -268,7 +268,7 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
if ( !If_CutMergeOrdered( p, pCut0, pCut1, pCut ) )
continue;
}
if ( p->pPars->fAcd && p->useLimitAdc && pCut->nLeaves > 6 )
if ( p->pPars->fUserLutDec && !fFirst && pCut->nLeaves > p->pPars->nLutDecSize )
continue;
if ( pObj->fSpec && pCut->nLeaves == (unsigned)p->pPars->nLutSize )
continue;
@ -429,9 +429,9 @@ void If_ObjPerformMappingAnd( If_Man_t * p, If_Obj_t * pObj, int Mode, int fPrep
pCut->Delay = If_CutDsdBalanceEval( p, pCut, NULL );
else if ( p->pPars->fUserRecLib )
pCut->Delay = If_CutDelayRecCost3( p, pCut, pObj );
else if ( p->pPars->fAcd )
else if ( p->pPars->fUserLutDec )
{
pCut->Delay = If_AcdEval( p, pCut, pObj, Mode == 0, fFirst );
pCut->Delay = If_LutDecEval( p, pCut, pObj, Mode == 0, fFirst );
pCut->fUseless = pCut->Delay == ABC_INFINITY;
}
else if ( p->pPars->fUserSesLib )
@ -518,7 +518,7 @@ void If_ObjPerformMappingChoice( If_Man_t * p, If_Obj_t * pObj, int Mode, int fP
If_Set_t * pCutSet;
If_Obj_t * pTemp;
If_Cut_t * pCutTemp, * pCut;
int i, fSave0 = p->pPars->fDelayOpt || p->pPars->fDelayOptLut || p->pPars->fDsdBalance || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fUse34Spec || p->pPars->fAcd;
int i, fSave0 = p->pPars->fDelayOpt || p->pPars->fDelayOptLut || p->pPars->fDsdBalance || p->pPars->fUserRecLib || p->pPars->fUserSesLib || p->pPars->fUse34Spec || p->pPars->fUserLutDec;
assert( pObj->pEquiv != NULL );
// prepare

4
src/map/if/ifTime.c
View File

@ -211,11 +211,11 @@ void If_CutPropagateRequired( If_Man_t * p, If_Obj_t * pObj, If_Cut_t * pCut, fl
pLeaf->Required = IF_MIN( pLeaf->Required, Required - pLutDelays[0] );
}
}
else if ( p->pPars->fAcd )
else if ( p->pPars->fUserLutDec )
{
Required = ObjRequired;
If_CutForEachLeaf( p, pCut, pLeaf, i )
pLeaf->Required = IF_MIN( pLeaf->Required, Required - If_AcdLeafProp( p, pCut, i, ObjRequired ) );
pLeaf->Required = IF_MIN( pLeaf->Required, Required - If_LutDecPinRequired( p, pCut, i, ObjRequired ) );
}
else
{