Angelo Jacobo
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e97dae7d5b
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Update README.md
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2023-06-22 20:01:01 +08:00 |
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AngeloJacobo
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b0e3b83e96
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added wb properties from zipcpu repo
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2023-06-22 19:54:39 +08:00 |
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AngeloJacobo
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d93cf9fb4e
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fixed delay for data mask as same delay as dq
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2023-06-22 19:53:37 +08:00 |
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AngeloJacobo
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ef10bfd455
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add data mask port
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2023-06-22 19:52:45 +08:00 |
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AngeloJacobo
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272711762e
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add phy for data mask (oserdes -> odelay -> obuf)
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2023-06-22 19:51:06 +08:00 |
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AngeloJacobo
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0ffdacf6e7
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add logic for write wb_ack, wb_sel, and aux
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2023-06-22 19:49:05 +08:00 |
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AngeloJacobo
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f4b138ff77
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Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main
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2023-06-22 19:45:16 +08:00 |
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AngeloJacobo
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96f4edd3e8
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add wb properties module
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2023-06-22 19:44:37 +08:00 |
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Angelo Jacobo
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4cb3b4a4b5
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Update README.md
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2023-06-15 18:54:42 +08:00 |
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Angelo Jacobo
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4786c77176
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Update temp.log
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2023-06-15 18:52:08 +08:00 |
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AngeloJacobo
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a98364dd1e
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added gtkw for formal
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2023-06-15 17:46:58 +08:00 |
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AngeloJacobo
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1937d34565
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create test 1(sequential access to first,middle,last rows) and test 2(random access)
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2023-06-15 17:46:14 +08:00 |
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AngeloJacobo
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0923fdc0b6
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add formal assertions using fifo to prove every wb request has a corresponding read/write command output
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2023-06-15 17:43:15 +08:00 |
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AngeloJacobo
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fd897b76bb
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update size of command_used
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2023-06-15 17:33:09 +08:00 |
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AngeloJacobo
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7c8b8af71f
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add minimum depth requirement for possible clock periods
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2023-06-15 17:24:48 +08:00 |
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AngeloJacobo
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60c9d5ae85
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added command type to be displayed in ASCII, changed all to posedge
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2023-06-10 08:41:37 +08:00 |
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AngeloJacobo
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acedb1310b
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added delay counters for debugging
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2023-06-10 08:40:13 +08:00 |
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AngeloJacobo
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366238b374
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Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main
add readme changes
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2023-06-10 08:27:45 +08:00 |
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AngeloJacobo
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053a511144
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set write-to-read delay for all banks for every write
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2023-06-10 08:19:16 +08:00 |
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Angelo Jacobo
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f80837491d
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Update README.md
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2023-06-08 14:16:27 +08:00 |
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Angelo Jacobo
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0bdef3092e
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Create temp.log for sim output
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2023-06-08 14:12:40 +08:00 |
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AngeloJacobo
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806b49ebd5
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changed folder name with underscore
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2023-06-08 14:05:35 +08:00 |
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AngeloJacobo
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f3e15e9ea4
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added test 1: Sequential write then sequential read
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2023-06-08 13:56:54 +08:00 |
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AngeloJacobo
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2e6c2183aa
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added sim duration for possible bus delays
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2023-06-08 13:55:20 +08:00 |
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AngeloJacobo
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de37c5a972
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added wires for loadingg delay tap
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2023-06-08 13:53:07 +08:00 |
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AngeloJacobo
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b9204332b1
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made delay tap loadable
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2023-06-08 13:52:04 +08:00 |
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AngeloJacobo
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c3707dab53
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made delay tap loadable and made delay more flexible to use all 32 taps for both dqs and dq
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2023-06-08 11:01:56 +08:00 |
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AngeloJacobo
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0e5d95098e
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added more pins to be debugged
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2023-06-08 10:55:32 +08:00 |
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Angelo Jacobo
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710d477014
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added vivado gtkw for micron model simulation
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2023-06-03 14:31:29 +08:00 |
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Angelo Jacobo
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98ed92a65b
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added testbench for a single ddr3 device sim
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2023-06-03 14:28:55 +08:00 |
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Angelo Jacobo
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9a19f82377
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added testbench for model simulation
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2023-06-03 14:24:11 +08:00 |
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Angelo Jacobo
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884fd2bcad
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Add files via upload
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2023-06-01 19:59:45 +08:00 |
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Angelo Jacobo
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35c992d6fd
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uploaded model.log
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2023-06-01 19:30:16 +08:00 |
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Angelo Jacobo
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748274ffff
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Update README.md
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2023-06-01 19:27:25 +08:00 |
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Angelo Jacobo
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6127bba77a
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fixed data alignment for write operation, fixed CL and CWL for 100MHz:400MHz clk
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2023-06-01 19:18:41 +08:00 |
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Angelo Jacobo
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26af4960e9
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fixed display for prev_cmd and time difference
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2023-06-01 19:15:36 +08:00 |
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Angelo Jacobo
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0a43b04f9e
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added phy for generating differential o_ddr3_clk
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2023-05-29 21:51:48 +08:00 |
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Angelo Jacobo
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d6b6c0b9a4
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added o_ddr3_clk port
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2023-05-29 21:48:44 +08:00 |
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Angelo Jacobo
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d674b1c9c2
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added autofpga text file for including the controller
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2023-05-29 20:59:12 +08:00 |
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Angelo Jacobo
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9e529131c0
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fixed error "added_read_pipe has multiple drivers"
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2023-05-29 20:52:48 +08:00 |
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Angelo Jacobo
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a56e6a8a24
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changed write calibration pattern with high autocorrel stat
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2023-05-29 16:40:41 +08:00 |
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Angelo Jacobo
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400a277cdc
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added 52ns sync reset (IDELAYCTRL requirement)
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2023-05-29 16:19:32 +08:00 |
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Angelo Jacobo
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f4f0a5c11c
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Update run.sh with the new ddr3 files
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2023-05-28 16:24:22 +08:00 |
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Angelo Jacobo
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7480704b3d
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Delete kluster.xdc
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2023-05-28 16:21:43 +08:00 |
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Angelo Jacobo
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02d512df55
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Delete sdram.txt
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2023-05-28 16:20:52 +08:00 |
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Angelo Jacobo
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12b533a9d1
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added top module which instantiates the controller and phy
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2023-05-28 16:20:22 +08:00 |
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Angelo Jacobo
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f648035e4e
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added phy interface (separated from controller)
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2023-05-28 16:19:47 +08:00 |
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Angelo Jacobo
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ab26902f7a
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include only the controller (phy is now a separate module)
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2023-05-28 16:18:14 +08:00 |
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Angelo Jacobo
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854839dde9
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readme file from Micron
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2023-05-28 16:14:21 +08:00 |
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Angelo Jacobo
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b9154a38bb
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Delete rtl/DDR3 directory
clean-up the repo
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2023-05-28 16:11:49 +08:00 |