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UberDDR3
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added o_ddr3_clk port

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Angelo Jacobo 2023-05-29 21:48:44 +08:00 committed by GitHub
parent d674b1c9c2
commit d6b6c0b9a4
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rtl/ddr3_top.v
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@ -36,6 +36,7 @@ module ddr3_top #(
output wire[wb_data_bits - 1:0] o_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device
output wire o_aux, //for AXI-interface compatibility (returned upon ack)
// DDR3 I/O Interface
output wire o_ddr3_clk_p, o_ddr3_clk_n,
output wire o_ddr3_reset_n,
output wire o_ddr3_cke, // CKE
output wire o_ddr3_cs_n, // chip select signal
@ -133,6 +134,8 @@ module ddr3_top #(
.o_controller_iserdes_bitslip_reference(iserdes_bitslip_reference),
.o_controller_idelayctrl_rdy(idelayctrl_rdy),
// DDR3 I/O Interface
.o_ddr3_clk_p(o_ddr3_clk_p),
.o_ddr3_clk_n(o_ddr3_clk_n),
.o_ddr3_reset_n(o_ddr3_reset_n),
.o_ddr3_cke(o_ddr3_cke), // CKE
.o_ddr3_cs_n(o_ddr3_cs_n), // chip select signal