added wires for loadingg delay tap
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@ -62,7 +62,10 @@ module ddr3_top #(
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wire[LANES*8-1:0] iserdes_dqs;
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wire[LANES*8-1:0] iserdes_bitslip_reference;
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wire idelayctrl_rdy;
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wire[4:0] odelay_data_cntvaluein, odelay_dqs_cntvaluein;
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wire[4:0] idelay_data_cntvaluein, idelay_dqs_cntvaluein;
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wire[LANES-1:0] odelay_data_ld, odelay_dqs_ld;
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wire[LANES-1:0] idelay_data_ld, idelay_dqs_ld;
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//module instantiations
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ddr3_controller #(
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.ROW_BITS(ROW_BITS), //width of row address
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@ -100,10 +103,14 @@ module ddr3_top #(
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.o_phy_dq_tri_control(dq_tri_control),
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.o_phy_toggle_dqs(toggle_dqs),
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.o_phy_data(data),
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.o_phy_odelay_ce(odelay_ce),
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.o_phy_odelay_inc(odelay_inc),
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.o_phy_idelay_ce(idelay_ce),
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.o_phy_idelay_inc(idelay_inc),
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.o_phy_odelay_data_cntvaluein(odelay_data_cntvaluein),
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.o_phy_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
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.o_phy_idelay_data_cntvaluein(idelay_data_cntvaluein),
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.o_phy_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
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.o_phy_odelay_data_ld(odelay_data_ld),
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.o_phy_odelay_dqs_ld(odelay_dqs_ld),
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.o_phy_idelay_data_ld(idelay_data_ld),
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.o_phy_idelay_dqs_ld(idelay_dqs_ld),
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.o_phy_bitslip(bitslip)
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);
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ddr3_phy #(
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@ -124,10 +131,14 @@ module ddr3_top #(
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.i_controller_dq_tri_control(dq_tri_control),
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.i_controller_toggle_dqs(toggle_dqs),
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.i_controller_data(data),
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.i_controller_odelay_ce(odelay_ce),
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.i_controller_odelay_inc(odelay_inc),
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.i_controller_idelay_ce(idelay_ce),
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.i_controller_idelay_inc(idelay_inc),
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.i_controller_odelay_data_cntvaluein(odelay_data_cntvaluein),
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.i_controller_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
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.i_controller_idelay_data_cntvaluein(idelay_data_cntvaluein),
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.i_controller_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
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.i_controller_odelay_data_ld(odelay_data_ld),
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.i_controller_odelay_dqs_ld(odelay_dqs_ld),
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.i_controller_idelay_data_ld(idelay_data_ld),
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.i_controller_idelay_dqs_ld(idelay_dqs_ld),
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.i_controller_bitslip(bitslip),
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.o_controller_iserdes_data(iserdes_data),
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.o_controller_iserdes_dqs(iserdes_dqs),
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