added vivado gtkw for micron model simulation
This commit is contained in:
Angelo Jacobo
GitHub
parent
98ed92a65b
commit
710d477014
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<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="ddr3_dimm_micron_sim_behav.wdb" id="1">
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<top_modules>
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<top_module name="ddr3_dimm_micron_sim" />
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<top_module name="glbl" />
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</top_modules>
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</db_ref>
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</db_ref_list>
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<zoom_setting>
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<ZoomStartTime time="55,535.400 ns"></ZoomStartTime>
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<ZoomEndTime time="55,594.601 ns"></ZoomEndTime>
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<Cursor1Time time="55,547.300 ns"></Cursor1Time>
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</zoom_setting>
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<column_width_setting>
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<NameColumnWidth column_width="247"></NameColumnWidth>
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<ValueColumnWidth column_width="66"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="40" />
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<wvobject fp_name="divider869" type="divider">
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<obj_property name="label">Model File</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_controller_clk">
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<obj_property name="ElementShortName">i_controller_clk</obj_property>
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<obj_property name="ObjectShortName">i_controller_clk</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk">
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<obj_property name="ElementShortName">i_ddr3_clk</obj_property>
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<obj_property name="ObjectShortName">i_ddr3_clk</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ref_clk">
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<obj_property name="ElementShortName">i_ref_clk</obj_property>
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<obj_property name="ObjectShortName">i_ref_clk</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_rst_n">
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<obj_property name="ElementShortName">i_rst_n</obj_property>
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<obj_property name="ObjectShortName">i_rst_n</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_wb_cyc">
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<obj_property name="ElementShortName">i_wb_cyc</obj_property>
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<obj_property name="ObjectShortName">i_wb_cyc</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_wb_stb">
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<obj_property name="ElementShortName">i_wb_stb</obj_property>
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<obj_property name="ObjectShortName">i_wb_stb</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_wb_we">
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<obj_property name="ElementShortName">i_wb_we</obj_property>
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<obj_property name="ObjectShortName">i_wb_we</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/i_wb_addr">
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<obj_property name="ElementShortName">i_wb_addr[23:0]</obj_property>
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<obj_property name="ObjectShortName">i_wb_addr[23:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/i_wb_data">
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<obj_property name="ElementShortName">i_wb_data[511:0]</obj_property>
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<obj_property name="ObjectShortName">i_wb_data[511:0]</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/o_wb_stall">
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<obj_property name="ElementShortName">o_wb_stall</obj_property>
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<obj_property name="ObjectShortName">o_wb_stall</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/o_wb_ack">
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<obj_property name="ElementShortName">o_wb_ack</obj_property>
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<obj_property name="ObjectShortName">o_wb_ack</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/o_wb_data">
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<obj_property name="ElementShortName">o_wb_data[511:0]</obj_property>
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<obj_property name="ObjectShortName">o_wb_data[511:0]</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ck_en">
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<obj_property name="ElementShortName">ck_en</obj_property>
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<obj_property name="ObjectShortName">ck_en</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/cs_n">
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<obj_property name="ElementShortName">cs_n</obj_property>
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<obj_property name="ObjectShortName">cs_n</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/odt">
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<obj_property name="ElementShortName">odt</obj_property>
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<obj_property name="ObjectShortName">odt</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ras_n">
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<obj_property name="ElementShortName">ras_n</obj_property>
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<obj_property name="ObjectShortName">ras_n</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/cas_n">
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<obj_property name="ElementShortName">cas_n</obj_property>
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<obj_property name="ObjectShortName">cas_n</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/we_n">
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<obj_property name="ElementShortName">we_n</obj_property>
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<obj_property name="ObjectShortName">we_n</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/reset_n">
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<obj_property name="ElementShortName">reset_n</obj_property>
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<obj_property name="ObjectShortName">reset_n</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/addr">
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<obj_property name="ElementShortName">addr[13:0]</obj_property>
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<obj_property name="ObjectShortName">addr[13:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ba_addr">
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<obj_property name="ElementShortName">ba_addr[2:0]</obj_property>
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<obj_property name="ObjectShortName">ba_addr[2:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/dq">
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<obj_property name="ElementShortName">dq[63:0]</obj_property>
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<obj_property name="ObjectShortName">dq[63:0]</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_controller_clk">
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<obj_property name="ElementShortName">i_controller_clk</obj_property>
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<obj_property name="ObjectShortName">i_controller_clk</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk">
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<obj_property name="ElementShortName">i_ddr3_clk</obj_property>
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<obj_property name="ObjectShortName">i_ddr3_clk</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/dqs">
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<obj_property name="ElementShortName">dqs[7:0]</obj_property>
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<obj_property name="ObjectShortName">dqs[7:0]</obj_property>
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<obj_property name="isExpanded"></obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/dqs_n">
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<obj_property name="ElementShortName">dqs_n[7:0]</obj_property>
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<obj_property name="ObjectShortName">dqs_n[7:0]</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/o_ddr3_clk_p">
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<obj_property name="ElementShortName">o_ddr3_clk_p</obj_property>
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<obj_property name="ObjectShortName">o_ddr3_clk_p</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/o_ddr3_clk_n">
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<obj_property name="ElementShortName">o_ddr3_clk_n</obj_property>
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<obj_property name="ObjectShortName">o_ddr3_clk_n</obj_property>
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</wvobject>
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<wvobject fp_name="divider870" type="divider">
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<obj_property name="label">DDR3 Controller</obj_property>
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<obj_property name="DisplayName">label</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/state_calibrate">
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<obj_property name="ElementShortName">state_calibrate[4:0]</obj_property>
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<obj_property name="ObjectShortName">state_calibrate[4:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/lane">
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<obj_property name="ElementShortName">lane[6:0]</obj_property>
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<obj_property name="ObjectShortName">lane[6:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/instruction_address">
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<obj_property name="ElementShortName">instruction_address[4:0]</obj_property>
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<obj_property name="ObjectShortName">instruction_address[4:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/dqs_store">
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<obj_property name="ElementShortName">dqs_store[39:0]</obj_property>
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<obj_property name="ObjectShortName">dqs_store[39:0]</obj_property>
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<obj_property name="Radix">BINARYRADIX</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/dqs_start_index">
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<obj_property name="ElementShortName">dqs_start_index[5:0]</obj_property>
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<obj_property name="ObjectShortName">dqs_start_index[5:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/dqs_start_index_repeat">
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<obj_property name="ElementShortName">dqs_start_index_repeat[0:0]</obj_property>
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<obj_property name="ObjectShortName">dqs_start_index_repeat[0:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/i_phy_iserdes_data">
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<obj_property name="ElementShortName">i_phy_iserdes_data[511:0]</obj_property>
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<obj_property name="ObjectShortName">i_phy_iserdes_data[511:0]</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/i_phy_iserdes_dqs">
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<obj_property name="ElementShortName">i_phy_iserdes_dqs[63:0]</obj_property>
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<obj_property name="ObjectShortName">i_phy_iserdes_dqs[63:0]</obj_property>
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<obj_property name="Radix">BINARYRADIX</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/i_phy_iserdes_bitslip_reference">
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<obj_property name="ElementShortName">i_phy_iserdes_bitslip_reference[63:0]</obj_property>
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<obj_property name="ObjectShortName">i_phy_iserdes_bitslip_reference[63:0]</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/i_phy_idelayctrl_rdy">
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<obj_property name="ElementShortName">i_phy_idelayctrl_rdy</obj_property>
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<obj_property name="ObjectShortName">i_phy_idelayctrl_rdy</obj_property>
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</wvobject>
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</wave_config>
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