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UberDDR3
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added gtkw for formal

This commit is contained in:
AngeloJacobo 2023-06-15 17:46:58 +08:00
parent 1937d34565
commit a98364dd1e
1 changed files with 238 additions and 0 deletions
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238
formal_cover_3.gtkw Normal file
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[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Wed Jun 14 09:17:49 2023
[*]
[dumpfile] "(null)"
[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal_cover_3.gtkw"
[timestart] 206
[size] 1848 1126
[pos] -1 -1
*-4.598215 307 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 391
[signals_width] 565
[sst_expanded] 1
[sst_vpaned_height] 743
@420
smt_step
@28
ddr3_controller.i_controller_clk
ddr3_controller.i_rst_n
ddr3_controller.reset_done
@24
ddr3_controller.state_calibrate[4:0]
@200
-
@28
ddr3_controller.o_wb_stall
ddr3_controller.o_wb_stall_d
ddr3_controller.i_wb_cyc
ddr3_controller.i_wb_stb
ddr3_controller.i_wb_we
@24
ddr3_controller.o_wb_ack
@28
ddr3_controller.o_wb_ack_read_q[15:0]
@200
-
@25
ddr3_controller.f_activate_slot[1:0]
ddr3_controller.f_precharge_slot[1:0]
ddr3_controller.f_read_slot[1:0]
ddr3_controller.f_write_slot[1:0]
@28
ddr3_controller.f_read_fifo
ddr3_controller.f_write_fifo
ddr3_controller.f_empty
ddr3_controller.f_full
ddr3_controller.f_read_pointer
ddr3_controller.f_write_pointer
ddr3_controller.shift_reg_read_pipe_d[4:0]
ddr3_controller.shift_reg_read_pipe_q[4:0]
ddr3_controller.write_calib_stb
ddr3_controller.write_calib_we
@200
-
@28
+{ddr3_controller.[PRE] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
@c00028
+{ddr3_controller.[ACT] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
@28
(0)ddr3_controller.cmd_d<1>[23:0]
(1)ddr3_controller.cmd_d<1>[23:0]
(2)ddr3_controller.cmd_d<1>[23:0]
(3)ddr3_controller.cmd_d<1>[23:0]
(4)ddr3_controller.cmd_d<1>[23:0]
(5)ddr3_controller.cmd_d<1>[23:0]
(6)ddr3_controller.cmd_d<1>[23:0]
(7)ddr3_controller.cmd_d<1>[23:0]
(8)ddr3_controller.cmd_d<1>[23:0]
(9)ddr3_controller.cmd_d<1>[23:0]
(10)ddr3_controller.cmd_d<1>[23:0]
(11)ddr3_controller.cmd_d<1>[23:0]
(12)ddr3_controller.cmd_d<1>[23:0]
(13)ddr3_controller.cmd_d<1>[23:0]
(14)ddr3_controller.cmd_d<1>[23:0]
(15)ddr3_controller.cmd_d<1>[23:0]
(16)ddr3_controller.cmd_d<1>[23:0]
(17)ddr3_controller.cmd_d<1>[23:0]
(18)ddr3_controller.cmd_d<1>[23:0]
(19)ddr3_controller.cmd_d<1>[23:0]
(20)ddr3_controller.cmd_d<1>[23:0]
(21)ddr3_controller.cmd_d<1>[23:0]
(22)ddr3_controller.cmd_d<1>[23:0]
(23)ddr3_controller.cmd_d<1>[23:0]
@1401200
-group_end
@c00028
+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
@28
(0)ddr3_controller.cmd_d<2>[23:0]
(1)ddr3_controller.cmd_d<2>[23:0]
(2)ddr3_controller.cmd_d<2>[23:0]
(3)ddr3_controller.cmd_d<2>[23:0]
(4)ddr3_controller.cmd_d<2>[23:0]
(5)ddr3_controller.cmd_d<2>[23:0]
(6)ddr3_controller.cmd_d<2>[23:0]
(7)ddr3_controller.cmd_d<2>[23:0]
(8)ddr3_controller.cmd_d<2>[23:0]
(9)ddr3_controller.cmd_d<2>[23:0]
(10)ddr3_controller.cmd_d<2>[23:0]
(11)ddr3_controller.cmd_d<2>[23:0]
(12)ddr3_controller.cmd_d<2>[23:0]
(13)ddr3_controller.cmd_d<2>[23:0]
(14)ddr3_controller.cmd_d<2>[23:0]
(15)ddr3_controller.cmd_d<2>[23:0]
(16)ddr3_controller.cmd_d<2>[23:0]
(17)ddr3_controller.cmd_d<2>[23:0]
(18)ddr3_controller.cmd_d<2>[23:0]
(19)ddr3_controller.cmd_d<2>[23:0]
(20)ddr3_controller.cmd_d<2>[23:0]
(21)ddr3_controller.cmd_d<2>[23:0]
(22)ddr3_controller.cmd_d<2>[23:0]
(23)ddr3_controller.cmd_d<2>[23:0]
@1401200
-group_end
@28
+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
ddr3_controller.issue_read_command
ddr3_controller.issue_write_command
@200
-
@28
ddr3_controller.bank_status_q[7:0]
@22
ddr3_controller.delay_before_write_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<7>[3:0]
ddr3_controller.delay_before_write_counter_q<7>[3:0]
ddr3_controller.delay_before_activate_counter_q<7>[3:0]
ddr3_controller.delay_before_write_counter_q<7>[3:0]
ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
@200
-
-
@22
ddr3_controller.delay_before_activate_counter_q<4>[3:0]
ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
ddr3_controller.delay_before_write_counter_q<4>[3:0]
@200
-
@28
ddr3_controller.cmd_odt
@24
ddr3_controller.instruction_address[4:0]
@28
ddr3_controller.pipe_stall
ddr3_controller.stage1_pending
ddr3_controller.stage1_we
ddr3_controller.stage2_pending
ddr3_controller.stage2_we
@24
ddr3_controller.stage1_bank[2:0]
ddr3_controller.stage2_bank[2:0]
@22
ddr3_controller.delay_before_write_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
@28
ddr3_controller.o_wb_stall_d
ddr3_controller.stage1_col[9:0]
@24
ddr3_controller.stage1_row[13:0]
ddr3_controller.stage2_row[13:0]
ddr3_controller.stage1_next_bank[2:0]
@c00024
ddr3_controller.stage1_next_row[13:0]
@28
(0)ddr3_controller.stage1_next_row[13:0]
(1)ddr3_controller.stage1_next_row[13:0]
(2)ddr3_controller.stage1_next_row[13:0]
(3)ddr3_controller.stage1_next_row[13:0]
(4)ddr3_controller.stage1_next_row[13:0]
(5)ddr3_controller.stage1_next_row[13:0]
(6)ddr3_controller.stage1_next_row[13:0]
(7)ddr3_controller.stage1_next_row[13:0]
(8)ddr3_controller.stage1_next_row[13:0]
(9)ddr3_controller.stage1_next_row[13:0]
(10)ddr3_controller.stage1_next_row[13:0]
(11)ddr3_controller.stage1_next_row[13:0]
(12)ddr3_controller.stage1_next_row[13:0]
(13)ddr3_controller.stage1_next_row[13:0]
@1401200
-group_end
@200
-
@22
ddr3_controller.delay_before_write_counter_q<0>[3:0]
ddr3_controller.delay_before_activate_counter_d<7>[3:0]
ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
@200
-
@22
ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
ddr3_controller.delay_before_precharge_counter_q<3>[3:0]
ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
ddr3_controller.delay_before_precharge_counter_q<5>[3:0]
ddr3_controller.delay_before_precharge_counter_q<6>[3:0]
ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
@200
-
@22
ddr3_controller.delay_before_read_counter_q<0>[3:0]
ddr3_controller.delay_before_read_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<2>[3:0]
ddr3_controller.delay_before_read_counter_q<3>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<5>[3:0]
@c00022
ddr3_controller.delay_before_read_counter_q<6>[3:0]
@28
(0)ddr3_controller.delay_before_read_counter_q<6>[3:0]
(1)ddr3_controller.delay_before_read_counter_q<6>[3:0]
(2)ddr3_controller.delay_before_read_counter_q<6>[3:0]
(3)ddr3_controller.delay_before_read_counter_q<6>[3:0]
@1401200
-group_end
@c00022
ddr3_controller.delay_before_read_counter_q<7>[3:0]
@28
(0)ddr3_controller.delay_before_read_counter_q<7>[3:0]
(1)ddr3_controller.delay_before_read_counter_q<7>[3:0]
(2)ddr3_controller.delay_before_read_counter_q<7>[3:0]
(3)ddr3_controller.delay_before_read_counter_q<7>[3:0]
@1401200
-group_end
@200
-
@24
ddr3_controller.bank_active_row_q<0>[13:0]
ddr3_controller.bank_active_row_q<1>[13:0]
ddr3_controller.bank_active_row_q<2>[13:0]
ddr3_controller.bank_active_row_q<3>[13:0]
ddr3_controller.bank_active_row_q<4>[13:0]
ddr3_controller.bank_active_row_q<5>[13:0]
ddr3_controller.bank_active_row_q<6>[13:0]
ddr3_controller.bank_active_row_q<7>[13:0]
[pattern_trace] 1
[pattern_trace] 0