AngeloJacobo
|
2a926cfc91
|
moved ARTY-S7 project files
|
2023-11-26 14:04:15 +08:00 |
|
AngeloJacobo
|
8d20a6f4d0
|
moved wcfg file inside testbench
|
2023-11-26 13:53:43 +08:00 |
|
AngeloJacobo
|
ba98139c56
|
changed the extension of all simulation files to systemverilog
|
2023-11-26 13:53:02 +08:00 |
|
AngeloJacobo
|
dcb48b75d3
|
changed the extension of all simulation files to systemverilog
|
2023-11-26 13:51:30 +08:00 |
|
AngeloJacobo
|
b54000f5f0
|
fix instantiation
|
2023-11-18 13:41:39 +08:00 |
|
AngeloJacobo
|
b9b49d67ab
|
add xdc file used to test controller in Arty-S7
|
2023-11-09 14:16:46 +08:00 |
|
AngeloJacobo
|
0b7d07e133
|
delete old bit and debug files
|
2023-11-09 14:14:27 +08:00 |
|
AngeloJacobo
|
2037044fb4
|
fixed reset logic of _top, changed address accessed by ~
|
2023-11-09 14:13:08 +08:00 |
|
AngeloJacobo
|
57e9f1b3f9
|
update simulation files
|
2023-09-15 20:04:55 +08:00 |
|
AngeloJacobo
|
0ba4f433e5
|
add delay option to misalign dq from dqs
|
2023-09-15 20:02:05 +08:00 |
|
AngeloJacobo
|
fd443ddefd
|
add wb2 width
|
2023-08-20 13:23:48 +08:00 |
|
AngeloJacobo
|
a8aec13ed9
|
using different address now finally works!
|
2023-08-20 11:52:54 +08:00 |
|
AngeloJacobo
|
5df83b8182
|
added working bitfiles for arty s7
|
2023-08-20 11:20:41 +08:00 |
|
AngeloJacobo
|
989e8dd9e7
|
use macro for defining the ddr3 config (EIGHT_LANES_x8 or TWO_LANES_x8) and the source of clk (if clock wizard or not)
|
2023-08-20 11:13:50 +08:00 |
|
AngeloJacobo
|
7c68bee5e8
|
changed for x8 config
|
2023-08-20 11:10:15 +08:00 |
|
AngeloJacobo
|
e839e220c3
|
ddr3 model fails when ROW_BITS less than 16 (has Z value in address)
|
2023-08-17 11:42:09 +08:00 |
|
AngeloJacobo
|
c97e5a8c1f
|
added test for testing design in ARTY-S7
|
2023-08-17 11:40:41 +08:00 |
|
AngeloJacobo
|
c9b19ac887
|
added uart submodule
|
2023-08-17 11:36:15 +08:00 |
|
AngeloJacobo
|
a8bf429bc8
|
allow tdqs off and use dm
|
2023-08-15 21:17:13 +08:00 |
|
AngeloJacobo
|
bc66655ca7
|
just fixed delay
|
2023-08-04 07:54:20 +08:00 |
|
AngeloJacobo
|
d2ae29c26a
|
simulation file for SODIMM
|
2023-07-24 17:34:40 +08:00 |
|
AngeloJacobo
|
4e5b98f485
|
use SODIMM instead of DIMM in simulation
|
2023-07-24 17:32:56 +08:00 |
|
AngeloJacobo
|
487b026f6c
|
add test to wb2
|
2023-07-19 18:50:23 +08:00 |
|
AngeloJacobo
|
4f857e08f4
|
add files back after git rm -r cached .
|
2023-07-16 08:46:16 +08:00 |
|
AngeloJacobo
|
4273a172f5
|
add wishbone 2 interface
|
2023-07-13 18:57:35 +08:00 |
|
AngeloJacobo
|
29ef663d87
|
set parameter FLY_BY_DELAY for each instantiated ddr3, the delay value is retrieved from 8192Mb_ddr3_parameters.vh
|
2023-07-13 18:55:57 +08:00 |
|
AngeloJacobo
|
6655959514
|
set different fly_by_delays for each lanes
|
2023-07-13 18:54:25 +08:00 |
|
AngeloJacobo
|
ecb4cb5b2c
|
moved FLY_BY_DELAY to this module so multiple instantiated ddr3 can have different set FLY_BY_DELAY
|
2023-07-13 18:52:43 +08:00 |
|
AngeloJacobo
|
a4d4e3a099
|
change all to non-blocking
|
2023-07-06 20:32:12 +08:00 |
|
AngeloJacobo
|
ab17b8012b
|
add average rate in report
|
2023-07-05 16:44:31 +08:00 |
|
AngeloJacobo
|
ba00cb9063
|
changed to non-blocking simulation
|
2023-06-29 12:59:57 +08:00 |
|
AngeloJacobo
|
4ecf119454
|
add error injections and use aux to determine ack request type
|
2023-06-24 07:56:05 +08:00 |
|
AngeloJacobo
|
d93cf9fb4e
|
fixed delay for data mask as same delay as dq
|
2023-06-22 19:53:37 +08:00 |
|
AngeloJacobo
|
1937d34565
|
create test 1(sequential access to first,middle,last rows) and test 2(random access)
|
2023-06-15 17:46:14 +08:00 |
|
AngeloJacobo
|
60c9d5ae85
|
added command type to be displayed in ASCII, changed all to posedge
|
2023-06-10 08:41:37 +08:00 |
|
AngeloJacobo
|
806b49ebd5
|
changed folder name with underscore
|
2023-06-08 14:05:35 +08:00 |