AngeloJacobo
|
ce3ca7e158
|
pre-refresh delay is now flexible and not fixed. Separated formal properties for testing time parameters
|
2023-07-05 16:35:57 +08:00 |
|
AngeloJacobo
|
217770b977
|
verified precharge and activate cmds, fixed bug in write_calib cmd
|
2023-07-02 06:38:33 +08:00 |
|
AngeloJacobo
|
3c32501ffd
|
log before passing fwb_slave
|
2023-06-29 19:37:49 +08:00 |
|
AngeloJacobo
|
bf7f9142b8
|
log after passing fwb_slave
|
2023-06-29 19:24:06 +08:00 |
|
AngeloJacobo
|
d6f9614295
|
update gtkw
|
2023-06-29 13:03:08 +08:00 |
|
AngeloJacobo
|
3251dda112
|
added gtkw for cover
|
2023-06-29 13:00:52 +08:00 |
|
AngeloJacobo
|
ba00cb9063
|
changed to non-blocking simulation
|
2023-06-29 12:59:57 +08:00 |
|
AngeloJacobo
|
188b26ee12
|
assume no request when slave busy (calibration or at refresh)
|
2023-06-29 12:58:41 +08:00 |
|
AngeloJacobo
|
2ca5a15c30
|
add cover
|
2023-06-29 12:56:58 +08:00 |
|
AngeloJacobo
|
760c75d238
|
passes optimized pipeline stall control and passed fwb_slave properties
|
2023-06-29 12:56:24 +08:00 |
|
AngeloJacobo
|
463707a07c
|
sim log before passing fwb_slave
|
2023-06-28 21:16:56 +08:00 |
|
AngeloJacobo
|
2cfbba6d28
|
change ff to unix
|
2023-06-24 08:04:21 +08:00 |
|
AngeloJacobo
|
6f90bc165c
|
passes all test with no violations
|
2023-06-24 07:59:05 +08:00 |
|
AngeloJacobo
|
4ecf119454
|
add error injections and use aux to determine ack request type
|
2023-06-24 07:56:05 +08:00 |
|
AngeloJacobo
|
c9e29935a0
|
add more pins in gtkw
|
2023-06-24 07:54:17 +08:00 |
|
AngeloJacobo
|
310f2d5af8
|
update wcfg
|
2023-06-24 07:53:28 +08:00 |
|
AngeloJacobo
|
a42a13ecab
|
Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main
|
2023-06-24 07:52:02 +08:00 |
|
AngeloJacobo
|
2221a739db
|
add 2 clocks in prestall delay to pass tWR violation, add more asserts for fwb_slave
|
2023-06-24 07:46:09 +08:00 |
|
Angelo Jacobo
|
e97dae7d5b
|
Update README.md
|
2023-06-22 20:01:01 +08:00 |
|
AngeloJacobo
|
b0e3b83e96
|
added wb properties from zipcpu repo
|
2023-06-22 19:54:39 +08:00 |
|
AngeloJacobo
|
d93cf9fb4e
|
fixed delay for data mask as same delay as dq
|
2023-06-22 19:53:37 +08:00 |
|
AngeloJacobo
|
ef10bfd455
|
add data mask port
|
2023-06-22 19:52:45 +08:00 |
|
AngeloJacobo
|
272711762e
|
add phy for data mask (oserdes -> odelay -> obuf)
|
2023-06-22 19:51:06 +08:00 |
|
AngeloJacobo
|
0ffdacf6e7
|
add logic for write wb_ack, wb_sel, and aux
|
2023-06-22 19:49:05 +08:00 |
|
AngeloJacobo
|
f4b138ff77
|
Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main
|
2023-06-22 19:45:16 +08:00 |
|
AngeloJacobo
|
96f4edd3e8
|
add wb properties module
|
2023-06-22 19:44:37 +08:00 |
|
Angelo Jacobo
|
4cb3b4a4b5
|
Update README.md
|
2023-06-15 18:54:42 +08:00 |
|
Angelo Jacobo
|
4786c77176
|
Update temp.log
|
2023-06-15 18:52:08 +08:00 |
|
AngeloJacobo
|
a98364dd1e
|
added gtkw for formal
|
2023-06-15 17:46:58 +08:00 |
|
AngeloJacobo
|
1937d34565
|
create test 1(sequential access to first,middle,last rows) and test 2(random access)
|
2023-06-15 17:46:14 +08:00 |
|
AngeloJacobo
|
0923fdc0b6
|
add formal assertions using fifo to prove every wb request has a corresponding read/write command output
|
2023-06-15 17:43:15 +08:00 |
|
AngeloJacobo
|
fd897b76bb
|
update size of command_used
|
2023-06-15 17:33:09 +08:00 |
|
AngeloJacobo
|
7c8b8af71f
|
add minimum depth requirement for possible clock periods
|
2023-06-15 17:24:48 +08:00 |
|
AngeloJacobo
|
60c9d5ae85
|
added command type to be displayed in ASCII, changed all to posedge
|
2023-06-10 08:41:37 +08:00 |
|
AngeloJacobo
|
acedb1310b
|
added delay counters for debugging
|
2023-06-10 08:40:13 +08:00 |
|
AngeloJacobo
|
366238b374
|
Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main
add readme changes
|
2023-06-10 08:27:45 +08:00 |
|
AngeloJacobo
|
053a511144
|
set write-to-read delay for all banks for every write
|
2023-06-10 08:19:16 +08:00 |
|
Angelo Jacobo
|
f80837491d
|
Update README.md
|
2023-06-08 14:16:27 +08:00 |
|
Angelo Jacobo
|
0bdef3092e
|
Create temp.log for sim output
|
2023-06-08 14:12:40 +08:00 |
|
AngeloJacobo
|
806b49ebd5
|
changed folder name with underscore
|
2023-06-08 14:05:35 +08:00 |
|
AngeloJacobo
|
f3e15e9ea4
|
added test 1: Sequential write then sequential read
|
2023-06-08 13:56:54 +08:00 |
|
AngeloJacobo
|
2e6c2183aa
|
added sim duration for possible bus delays
|
2023-06-08 13:55:20 +08:00 |
|
AngeloJacobo
|
de37c5a972
|
added wires for loadingg delay tap
|
2023-06-08 13:53:07 +08:00 |
|
AngeloJacobo
|
b9204332b1
|
made delay tap loadable
|
2023-06-08 13:52:04 +08:00 |
|
AngeloJacobo
|
c3707dab53
|
made delay tap loadable and made delay more flexible to use all 32 taps for both dqs and dq
|
2023-06-08 11:01:56 +08:00 |
|
AngeloJacobo
|
0e5d95098e
|
added more pins to be debugged
|
2023-06-08 10:55:32 +08:00 |
|
Angelo Jacobo
|
710d477014
|
added vivado gtkw for micron model simulation
|
2023-06-03 14:31:29 +08:00 |
|
Angelo Jacobo
|
98ed92a65b
|
added testbench for a single ddr3 device sim
|
2023-06-03 14:28:55 +08:00 |
|
Angelo Jacobo
|
9a19f82377
|
added testbench for model simulation
|
2023-06-03 14:24:11 +08:00 |
|
Angelo Jacobo
|
884fd2bcad
|
Add files via upload
|
2023-06-01 19:59:45 +08:00 |